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Sampath K Karikalan

from Irvine, CA
Age ~58

Sampath Karikalan Phones & Addresses

  • 7 Lexington, Irvine, CA 92620 (949) 872-2996
  • 1541 Carriage Ln, Chandler, AZ 85224 (480) 598-8786
  • 5352 Geronimo St, Chandler, AZ 85226 (480) 598-8786
  • Phoenix, AZ
  • Ladera Ranch, CA
  • Maricopa, AZ
  • 5352 W Geronimo St, Chandler, AZ 85226 (480) 797-7890

Work

Position: Transportation and Material Moving Occupations

Education

Degree: High school graduate or higher

Emails

Publications

Us Patents

Apparatus And Method Of Packaging Two Dimensional Photonic Array Devices

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US Patent:
20040120658, Jun 24, 2004
Filed:
Dec 19, 2002
Appl. No.:
10/325259
Inventors:
Jonathan McFarland - Phoenix AZ, US
Suresh Golwalkar - Phoenix AZ, US
Sampath Karikalan - Chandler AZ, US
Kevin Cote - Chandler AZ, US
Wu Chou - Chandler AZ, US
International Classification:
G02B006/43
US Classification:
385/089000
Abstract:
An optical coupler for forming an optical connection between one or more two dimensional photonic array devices and an optical fiber and for forming an electrical connection between the two dimensional photonic array devices and a substrate, a system including the optical coupler and materials, and methods of forming the optical coupler and system are disclosed. The optical coupler includes a light transmission medium and electrical connectors, which are at least partially encapsulated. In addition, the device includes alignment guides configured to receive guide pins from a fiber optic connector, such that when the fiber optic connector is attached to the optical coupler, fibers of the ribbon align with the two dimensional photonic array device(s) via the light transmission medium.

Stacked Packaging Using Reconstituted Wafers

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US Patent:
20130154106, Jun 20, 2013
Filed:
Dec 14, 2011
Appl. No.:
13/325951
Inventors:
Kevin Kunzhong Hu - Irvine CA, US
Sam Ziqun Zhao - Irvine CA, US
Rezaur Rahman Khan - Rancho Santa Margarita CA, US
Pieter Vorenkamp - Laguna Niguel CA, US
Sampath K.V. Karikalan - Irvine CA, US
Xiangdong Chen - Irvine CA, US
Assignee:
BROADCOM CORPORATION - IRVINE CA
International Classification:
H01L 23/498
H01L 21/78
US Classification:
257774, 438113, 257E23067, 257E21599
Abstract:
An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement.

Programmable Interposer With Conductive Particles

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US Patent:
20130168841, Jul 4, 2013
Filed:
Dec 29, 2011
Appl. No.:
13/340430
Inventors:
Sam Ziqun Zhao - Irvine CA, US
Kevin Kunzhong Hu - Irvine CA, US
Sampath K.V. Karikalan - Irvine CA, US
Rezaur Rahman Khan - Rancho Santa Margarita CA, US
Pieter Vorenkamp - Laguna Niguel CA, US
Xiangdong Chen - Irvine CA, US
International Classification:
H01L 23/495
H01L 21/326
H05K 1/11
B82Y 99/00
US Classification:
257676, 174261, 438468, 977742, 257E23037, 257E21327
Abstract:
An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable interposer. The conductive particles are capable of forming an aligned configuration between the top and bottom interface electrodes in response to application of an energy field to the programmable interposer so as to electrically connect the top and bottom interface electrodes. The conductive particles can have a conductive outer surface. Also, the conductive particles can be spherical. The conductive particles can be within a bulk material in an interface layer in the programmable interposer, and the bulk material can be cured to secure programmed paths between the top and bottom interface electrodes.

Semiconductor Package With A Bridge Interposer

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US Patent:
20130168854, Jul 4, 2013
Filed:
Dec 28, 2011
Appl. No.:
13/339266
Inventors:
Sampath K.V. KARIKALAN - Irvine CA, US
Sam Ziqun ZHAO - Irvine CA, US
Kevin Kunzhong HU - Irvine CA, US
Rezaur Rahman KHAN - Rancho Santa Margarita CA, US
Pieter VORENKAMP - Laguna Niguel CA, US
Xiangdong CHEN - Irvine CA, US
Assignee:
BROADCOM CORPORATION - Irvine CA
International Classification:
H01L 23/498
H01L 23/48
US Classification:
257738, 257784, 257E23069, 257E2301
Abstract:
There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs).

Semiconductor Package With Ultra-Thin Interposer Without Through-Semiconductor Vias

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US Patent:
20130168860, Jul 4, 2013
Filed:
Dec 28, 2011
Appl. No.:
13/339234
Inventors:
Sampath K.V. Karikalan - Irvine CA, US
Sam Ziqun Zhao - Irvine CA, US
Kevin Kunzhong Hu - Irvine CA, US
Rezaur Rahman Khan - Rancho Santa Margarita CA, US
Pieter Vorenkamp - Laguna Niguel CA, US
Xiangdong Chen - Irvine CA, US
Assignee:
BROADCOM CORPORATION - Irvine CA
International Classification:
H01L 23/538
H01L 23/532
US Classification:
257741, 257774, 257E23169, 257E23161
Abstract:
There are disclosed herein various implementations of semiconductor packages including an interposer without through-semiconductor vias (TSVs). One exemplary implementation includes a first active die situated over an interposer. The interposer includes an interposer dielectric having intra-interposer routing traces. The first active die communicates electrical signals to a package substrate situated below the interposer utilizing the intra-interposer routing traces and without utilizing TSVs. In one implementation, the semiconductor package includes a second active die situated over the interposer, the second active die communicating electrical signals to the package substrate utilizing the intra-interposer routing traces and without utilizing TSVs. Moreover, in one implementation, the first active die and the second active die communicate chip-to-chip signals through the interposer.

Semiconductor Interposer Having A Cavity For Intra-Interposer Die

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US Patent:
20130181354, Jul 18, 2013
Filed:
Jan 12, 2012
Appl. No.:
13/349045
Inventors:
Rezaur Rahman Khan - Rancho Santa Margarita CA, US
Sam Ziqun Zhao - Irvine CA, US
Pieter Vorenkamp - Laguna Niguel CA, US
Kevin Kunzhong Hu - Irvine CA, US
Sampath K.V. Karikalan - Irvine CA, US
Xiangdong Chen - Irvine CA, US
Assignee:
BROADCOM CORPORATION - Irvine CA
International Classification:
H01L 23/48
US Classification:
257774, 257E23011
Abstract:
A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate.

Semiconductor Package With Improved Testability

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US Patent:
20130193996, Aug 1, 2013
Filed:
Jan 31, 2012
Appl. No.:
13/362344
Inventors:
Sam Ziqun Zhao - Irvine CA, US
Kevin Kunzhong Hu - Irvine CA, US
Sampath K.V. Karikalan - Irvine CA, US
Rezaur Rahman Khan - Rancho Santa Margarita CA, US
Pieter Vorenkamp - Laguna Niguel CA, US
Xiangdong Chen - Irvine CA, US
Assignee:
BROADCOM CORPORATION - IRVINE CA
International Classification:
G01R 31/26
H01L 23/544
US Classification:
32476202, 257 48, 257E23179
Abstract:
An exemplary implementation of the present disclosure includes a testable semiconductor package that includes an active die having interface contacts and dedicated testing contacts. An interposer is situated adjacent a bottom surface of the active die, the interposer providing electrical connections between the interface contacts and a bottom surface of the testable semiconductor package. At least one conductive medium provides electrical connection between at least one of the dedicated testing contacts and a top surface of the testable semiconductor package. The at least one conductive medium can be coupled to a package-top testing connection, which may include a solder ball.

Semiconductor Package With Integrated Electromagnetic Shielding

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US Patent:
20130221499, Aug 29, 2013
Filed:
Feb 27, 2012
Appl. No.:
13/405721
Inventors:
Sampath K.V. Karikalan - Irvine CA, US
Kevin Kunzhong Hu - Irvine CA, US
Sam Ziqun Zhao - Irvine CA, US
Rezaur Rahman Khan - Rancho Santa Margarita CA, US
Pieter Vorenkamp - Laguna Niguel CA, US
Xiangdong Chen - Irvine CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H01L 23/552
US Classification:
257659, 257E23114
Abstract:
There are disclosed herein various implementations of a shield interposer situated between a top active die and a bottom active die for shielding the active dies from electromagnetic noise. One implementation includes an interposer dielectric layer, a through-silicon via (TSV) within the interposer dielectric layer, and an electromagnetic shield. The TSV connects the electromagnetic shield to a first fixed potential. The electromagnetic shield may include a grid of conductive layers laterally extending across the shield interposer. The shield interposer may also include another electromagnetic shield connected to another fixed potential.
Sampath K Karikalan from Irvine, CA, age ~58 Get Report