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Sajosh Janarthanam

from Hillsboro, OR
Age ~48
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Also known as:
Sajash Janarthanam, Sajosh Janarthenam, Sajosh Narthana, H Janarthanam, Sajosh M, Sajosh L
Phone and address:
1867 NE Ashberry Dr, Beaverton, OR 97124
Connected to:
Saranya N Janarthanan, 35Janusz Janas, 77Lisa A Janasek, 62Marek Janasek, 64Robert J Janasek, 67Thomas S Janasek, 31Jill M Janasiewicz, 56Praneeth S Janaswamy, 36Richard B Janaszek, 66Douglas R Janata, 57

Sajosh Janarthanam Phones & Addresses

  • 1867 NE Ashberry Dr, Hillsboro, OR 97124
  • Redwood City, CA
  • 5604 Southwest Dr, Austin, TX 78735
  • 12610 Riata Trace Pkwy, Austin, TX 78727
  • Milpitas, CA

Skills

Power Management • Team Management • Microprocessors • Verilog • RTL design • Microarchitecture • SoC • ASIC • IC • Semiconductors • Functional Verification • Processors • Debugging

Industries

Computer Hardware

Resumes

Resumes

Sajosh Janarthanam Photo 1

Sajosh Janarthanam

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Location:
United States
Industry:
Computer Hardware
Skills:
Power Management
Team Management
Microprocessors
Verilog
RTL design
Microarchitecture
SoC
ASIC
IC
Semiconductors
Functional Verification
Processors
Debugging

Publications

Us Patents

Error Detection In Fifo Queues Using Signature Bits

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US Patent:
8583971, Nov 12, 2013
Filed:
Dec 23, 2010
Appl. No.:
12/977338
Inventors:
Sajosh Janarthanam - Austin TX, US
Jonathan Owen - Northborough MA, US
Michael Osborn - Hollis NH, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G11C 29/00
US Classification:
714719, 714801, 714805
Abstract:
A first in, first out (FIFO) queue includes logic to provide detection of operational errors in the FIFO queue. The FIFO queue includes entries to store data written to the FIFO queue and signature bits, each signature bit corresponding to one of the entries. A test pattern and a read signature register includes a number of bits greater than a depth of the FIFO queue. A comparator compares the test pattern to the read signature register and output an error signal indicating whether the test pattern matches the read signature register.

Method Of Testing The Encryption Function Of A Device

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US Patent:
7328339, Feb 5, 2008
Filed:
Nov 3, 2003
Appl. No.:
10/699947
Inventors:
Sajosh Janarthanam - Austin TX, US
Kheng Guan (Nigel) Tan - Singapore, SG
Assignee:
Advanced Micro Devices Inc - Sunnyvale CA
International Classification:
H04L 9/00
US Classification:
713161, 713168, 713181, 380 37
Abstract:
A packet data string is provided to a device under test (DUT), which preprocesses the packet data string, based on static inputs, to provide packet segment data strings, which are placed in a queue in a memory structure. Separate therefrom, a packet segment data string is applied to an encryption engine of the DUT, which encryption engine has an initialization vector applied thereto, and an encryption algorithm of the encryption engine is applied to this packet segment data string to provide an encrypted packet segment data string. Bit length and initialization vector matching techniques are used to eliminate packet segment data strings in the queue from further consideration, and after bit length and initialization vector matching are achieved in regard to a packet segment data string in the queue, such packet segment data string is encrypted using the encryption algorithm and an initialization vector extracted from the previously encrypted packet segment data string, whereupon a bitwise comparison is made between the encrypted packet segment data strings.
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Sajosh Janarthanam from Hillsboro, OR, age ~48 Get Report