Sajitha S Wijesuriya

7183798, Feb 27, 2007

Jan 24, 2005

11/041319

Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Claudia Stanley - Austin TX, US
John Schadt - Bethlehem PA, US

Lattice Semiconductor Corporation - Hillsboro OR

H03K 19/173

326 38, 326 93, 36523005

Systems and methods are disclosed herein to provide improved memory techniques for logic blocks within a programmable logic device. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a first and a second logic slice adapted to receive a first and a second clock signal. The first and second logic slices may be combined to form wider and deeper memory and single port or synchronous dual port memory.

7196963, Mar 27, 2007

Oct 17, 2005

11/251682

Larry R. Fenstermaker - Nazareth PA, US
Sajitha Wijesuriya - Macungie PA, US
Harold N. Scholz - Allentown PA, US

Lattice Semiconductor Corporation - Hillsboro OR

G11C 8/00
G11C 7/10

36523005, 36518904, 36518908

In one embodiment of the invention, a block of configuration memory has rows of memory cells, at least one row having a set of one or more dual-port memory cells adapted to selectively store either configuration data or local data. The configuration address line for that row is segmented such that the address line is connected to the configuration address ports of the dual-port memory cells via access control circuitry that can be programmably configured to prevent access to those memory cells via the configuration address line. The access control circuitry enables local data to be efficiently and accurately stored in the dual-port memory cells without interference from configuration readback operations during normal operation or from partial reconfiguration of the configuration memory.

7378872, May 27, 2008

Jun 2, 2006

11/445620

Om P. Agrawal - Los Altos CA, US
Barry Britton - Orefield PA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US

Lattice Semiconductor Corporation - Hillsboro OR

H03K 19/177

326 41, 326 37, 326 38, 326 39, 326 47

Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks, with at least one of the programmable logic blocks having at least a first, a second, and a third logic block slice of different logic block slice types.

7385417, Jun 10, 2008

Jun 2, 2006

11/446542

Om P. Agrawal - Los Altos CA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Barry Britton - Orefield PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US

Lattice Semiconductor Corporation - Hillsboro OR

G06F 7/38
H03K 19/173

326 39, 326 41, 326 47

Systems and methods are disclosed herein to provide dual slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of dual-slice logic blocks within each of the programmable logic blocks, wherein each dual-slice logic block includes a first and a second slice each having at least a first lookup table, with a first one of the dual-slice logic blocks of a logic block slice type different from a second one of the dual-slice logic blocks, and a third one of the dual-slice logic blocks of a logic block slice type different from the first and second dual-slice logic blocks.

7397276, Jul 8, 2008

Jun 2, 2006

11/446351

Om P. Agrawal - Los Altos CA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Barry Britton - Orefield PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US

Lattice Semiconductor Corporation - Hillsboro OR

H03K 19/177

326 41, 326 38, 326 39, 326 47

Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks, with each of the logic block slices having at least a first and a second slice each having at least a first lookup table. At least one of the programmable logic blocks includes at least a first logic block slice, a second logic block slice, and a third logic block slice, with the first logic block slice being a logic block slice type different from the second logic block slice, and the third logic block slice being a logic block slice type different from the first and second logic block slices. Control logic provides at a programmable logic block level bundled and/or unbundled control signals at a logic block slice level for at least two of the logic block slices.

7592834, Sep 22, 2009

Jun 30, 2008

12/164265

Om P. Agrawal - Los Altos CA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Barry Britton - Orefield PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US

Lattice Semiconductor Corporation - Hillsboro OR

H03K 19/173

326 38, 326 40, 326 41, 326 47

In one embodiment of the invention, a programmable logic device comprises configuration memory adapted to store configuration data and a plurality of programmable logic blocks. At least one programmable logic block includes a plurality of dual-slice logic blocks, each dual-slice logic block including first and second slices, each slice including at least two lookup tables (LUTs) and a register. The programmable logic block further includes control logic adapted for selecting control signals separately at a programmable block level, a dual-slice block level, and a register level, the control logic responsive to configuration data stored within the configuration memory.

7605606, Oct 20, 2009

Aug 3, 2006

11/498646

Ming H. Ding - San Jose CA, US
Sajitha Wijesuriya - Macungie PA, US
Jun Zhao - Allentown PA, US
Om P. Agrawal - Los Altos CA, US
Barry Britton - Orefield PA, US
Xiaojie He - Austin TX, US

Lattice Semiconductor Corporation - Hillsboro OR

H03K 19/177

326 41, 326 38

Systems and methods provide programmable logic block architectures and routing architectures for the programmable logic blocks. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks. A first routing circuit provides global signal routing within the programmable logic device for the corresponding programmable logic block. A first input routing circuit receives signals from the first routing circuit and routes the signals to the logic block slices within the corresponding programmable logic block.

7675321, Mar 9, 2010

Mar 24, 2009

12/409757

Om P. Agrawal - Los Altos CA, US
Xiaojie He - Austin TX, US
Sajitha Wijesuriya - Macungie PA, US
Barry Britton - Orefield PA, US
Ming H. Ding - San Jose CA, US
Jun Zhao - Allentown PA, US

Lattice Semiconductor Corporation - Hillsboro OR

H01L 25/00
G06F 7/38

326 41, 326 38, 326 40, 326 47

In one embodiment of the invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of dual-slice logic blocks within a programmable logic block. A dual-slice logic block includes a first slice including at least two lookup tables (LUTs); a second slice including at least two LUTs; and a routing circuit coupled to each of the LUTs within the first and second slices. The routing circuit is adapted to share outputs of the dual-slice logic block among the LUTs. In another embodiment of the invention, the dual-slice logic block includes a second routing circuit coupled to each of the LUTs within the first and second slices. The second routing circuit is adapted to share inputs of the dual-slice logic block among the LUTs.