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Sachin D Dasnurkar

from Campbell, CA
Age ~43
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Also known as:
Sachin Dileep Dasnurkar
Phone and address:
1953 Villarita Dr, Campbell, CA 95008
Related to:
Raee R Nadkarni, 42
Connected to:
Mary Dasovich, 59Brandon S Daspit, 48Fay N Daspit, 62Kamla P Dasrath, 65Michael R Dasrath, 69Akash Dass, 50Amir S Dass, 49Chitra S Dass, 52Eric J Dass, 69Gurnam Dass, 57

Sachin Dasnurkar Phones & Addresses

  • 1953 Villarita Dr, Campbell, CA 95008
  • San Diego, CA
  • Cedar Park, TX
  • San Jose, CA
  • Austin, TX
  • Dallas, TX

Work

Company: Qualcomm 2008 Position: Product development engineer

Education

Degree: Doctor of Philosophy (Ph.D.) School / High School: The University of Texas at Austin 2008 to 2012 Specialities: Electrical and Computer Engineering

Skills

Asic • Soc • Dft • Verilog • Debugging • Semiconductors • Application Specific Integrated Circuits • System on A Chip • Vlsi • Mixed Signal • Cmos • Integrated Circuit Design • Integrated Circuits • Ic • Analog • Atpg • Power

Languages

English

Industries

Semiconductors

Resumes

Resumes

Sachin Dasnurkar Photo 1

Hardware And System Power Engineer

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Location:
1953 Villarita Dr, Campbell, CA 95008
Industry:
Semiconductors
Work:
Qualcomm since 2008
Product Development Engineer
Texas Instruments Jul 2006 - Jul 2008
Product Development Engineer
AMD Jan 2006 - May 2006
Product Engineering Intern
PulseWave RF 2005 - 2005
Summer Intern
Freescale Semiconductor 2005 - 2005
Fall Co-op
Education:
The University of Texas at Austin 2008 - 2012
Doctor of Philosophy (Ph.D.), Electrical and Computer Engineering The University of Texas at Austin 2004 - 2006
Master of Science (M.S.), Electrical and Computer Engineering University of Mumbai 2000 - 2004
BE, Electronics and Telecommunication
Skills:
Asic
Soc
Dft
Verilog
Debugging
Semiconductors
Application Specific Integrated Circuits
System on A Chip
Vlsi
Mixed Signal
Cmos
Integrated Circuit Design
Integrated Circuits
Ic
Analog
Atpg
Power
Languages:
English

Publications

Us Patents

Systems And Methods For Built In Self Test Jitter Measurement

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US Patent:
8283933, Oct 9, 2012
Filed:
Feb 17, 2010
Appl. No.:
12/707534
Inventors:
Sachin D Dasnurkar - San Diego CA, US
Assignee:
QUALCOMM, Incorporated - San Diego CA
International Classification:
G01R 29/26
US Classification:
324613, 324555, 375354, 327141, 327147, 702 69
Abstract:
An apparatus configured for built in self test (BIST) jitter measurement is described. The apparatus includes a time-to-voltage converter. The time-to-voltage converter generates a voltage signal proportional to timing jitter present in a clock/data signal input. The apparatus also includes feedback circuitry for the time-to-voltage converter. The feedback circuitry provides a ramp slope for the time-to-voltage converter. The apparatus further includes a calibration controller. The calibration controller provides control signals to the time-to-voltage converter for process-independent calibration. The apparatus also includes a sample-and-hold (S/H) circuit. The S/H circuit provides a set bias voltage to the time-to-voltage converter once calibration is complete.

Systems And Methods For Vector-Based Analog-To-Digital Converter Sequential Testing

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US Patent:
8310385, Nov 13, 2012
Filed:
May 10, 2010
Appl. No.:
12/777091
Inventors:
Sachin D. Dasnurkar - San Diego CA, US
Assignee:
QUALCOMM, Incorporated - San Diego CA
International Classification:
H03M 1/10
US Classification:
341120, 341155, 714718
Abstract:
A method for providing built-in self test (BiST) for an analog-to-digital converter (ADC) by automatic test equipment (ATE) is described. Output codes are received from the ADC. The output codes are translated to generate a functional pattern. Performance metrics are determined for the ADC using the functional pattern. The ADC may be on a device-under-test (DUT).

Real-Time Adaptive Hybrid Bist Solution For Low-Cost And Low-Resource Ate Production Testing Of Analog-To-Digital Converters

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US Patent:
8510073, Aug 13, 2013
Filed:
Nov 30, 2010
Appl. No.:
12/957277
Inventors:
Sachin D. Dasnurkar - San Diego CA, US
Assignee:
QUALCOMM, Incorporated - San Diego CA
International Classification:
H03M 1/10
US Classification:
702117
Abstract:
An integrated circuit configured to perform hybrid built in self test (BiST) of analog-to-digital converters (ADCs) is described. The integrated circuit includes an ADC. The integrated circuit also includes a BiST controller that controls the hybrid BiST. The integrated circuit further includes a ramp generator that provides a voltage ramp to the ADC. The integrated circuit also includes a first multiplexer that switches an input for the ADC between the voltage ramp and a voltage reference signal. The integrated circuit further includes feedback circuitry for the ramp generator that maintains a constant ramp slope for the ramp generator. The integrated circuit also includes an interval counter that provides a timing reference.

Methods And Apparatus For Built In Self Test Of Analog-To-Digital Convertors

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US Patent:
20100253559, Oct 7, 2010
Filed:
Feb 1, 2010
Appl. No.:
12/697435
Inventors:
Sachin D Dasnurkar - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H03M 1/10
US Classification:
341121
Abstract:
An apparatus configured for built in self test (BiST) of analog-to-digital convertors (ADCs) is described. The apparatus includes an ADC to be tested. The apparatus includes a ramp generator. The ramp generator provides a voltage ramp to the ADC. The apparatus further includes feedback circuitry for the ramp generator. The feedback circuitry maintains a constant ramp slope for the ramp generator. The apparatus includes an interval counter. The interval counter provides a timing reference.

Systems And Methods For A Phase Locked Loop Built In Self Test

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US Patent:
20100293426, Nov 18, 2010
Filed:
Apr 19, 2010
Appl. No.:
12/762985
Inventors:
Sachin D. Dasnurkar - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
G01R 31/3177
G06F 11/25
US Classification:
714733, 714E11155
Abstract:
An apparatus configured for a phase locked loop (PLL) built in self test (BIST) jitter measurement is described. The apparatus includes a phase detector. The phase detector produces a digital signal that describes a comparison between a reference signal and a feedback signal. The apparatus also includes a BIST controller. The BIST controller accumulates the digital signal with successive digital signals. The apparatus also includes a communication pin. The communication pin sends the accumulated signal to automatic test equipment (ATE) that determines whether the PLL is operating correctly based on the accumulated signal.

Automatic Failure Identification And Failure Pattern Identification Within An Ic Wafer

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US Patent:
20170242070, Aug 24, 2017
Filed:
Feb 23, 2016
Appl. No.:
15/051537
Inventors:
- San Diego CA, US
Sachin Dasnurkar - San Diego CA, US
International Classification:
G01R 31/30
G01R 31/28
Abstract:
Embodiments described herein provide a method for identifying failure patterns in electronic devices. The method begins when a limit is determined for a parameter of interest. A series of the electronic devices is then tested using the limit of the parameter of interest. Failing devices are then identified and x and y coordinate values are plotted. Pattern recognition may be used to determine if the failures shown on the coordinate plot fit a failure pattern. The limit of the parameter of interest is then regressed in steps to the mean value of the failing devices and the electronic devices are retested. The failure pattern of the retested devices is examined to determine if the failure pattern fits a failure pattern. If the failure pattern fits a failure pattern then the parameter of interest may be found to affect the yield rate of production for the electronic devices.

Algorithm For Preferred Core Sequencing To Maximize Performance And Reduce Chip Temperature And Power

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US Patent:
20150338902, Nov 26, 2015
Filed:
Jun 30, 2014
Appl. No.:
14/319393
Inventors:
- San Diego CA, US
Mehdi Saeidi - San Diego CA, US
Tao Xue - San Diego CA, US
Ronald Frank Alton - Oceanside CA, US
Rajit Chandra - San Diego CA, US
Sachin Dasnurkar - San Diego CA, US
International Classification:
G06F 1/32
Abstract:
Aspects include computing devices, systems, and methods for selecting preferred processor core combinations for a state of a computing device. In an aspect, a state of a computing device containing the multi-core processor may be determined. A number of current leakage ratios may be determined by comparing current leakages of the processor cores to current leakages of the other processor cores. The ratios may be compared to boundaries for the state of the computing device in respective inequalities. A processor core associated with a number of boundaries may be selected in response to determining that the respective inequalities are true. The boundaries may be associated with a set of processor cores deemed preferred for an associated state of the computing device. The processor core present in the set of processor cores for each boundary of a true inequality may be the selected processor core.

All-Digital Phase Locked Loop Self Test System

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US Patent:
20140225635, Aug 14, 2014
Filed:
Feb 11, 2013
Appl. No.:
13/764375
Inventors:
- San Diego CA, US
Sachin D. Dasnurkar - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
G01R 31/3187
US Classification:
3247503
Abstract:
A method and apparatus for an all-digital built in self test (BIST) of a phase locked loop includes a phase detector (PD), wherein the PD produces a digital signal describing a comparison between a reference signal and a feedback signal, and an all-digital programmable BIST coupled to the PD and a charge pump (CP). The BIST includes a digital counter to accumulate the digital signal, and a communication link, which provides the accumulated digital signal from the counter to automatic test equipment (ATE), which determines whether the PLL is operating correctly based on the accumulated digital signal. The method includes injecting signal pulses into the PLL to adjust a signal of the PLL, accumulating in a digital counter a digital signal that describes a comparison between the PLL feedback and reference signals, and determining whether the PLL is operating correctly based on the accumulated digital signal in the digital counter.
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Sachin D Dasnurkar from Campbell, CA, age ~43 Get Report