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Ryan N Rakvic

from Arnold, MD
Age ~49
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Also known as:
Ryan N Rakuiz, Ryan Rakvi, Ryan K
Phone and address:
106 Malier Dr, Arnold, MD 21012
(410) 757-4501
Related to:
Robert J JeffreyRaymond P RakvicJill A Rakvic, 47Lauren A Rakvic, 49Helen A Rakvic, 83Ryan N Rakuiz, 82Terrance L Smay, 75Raymond P Rakvic, 53Diana K Smay, 79
Connected to:
Marcos A Ralac, 45Carmen M Ralat, 88Jeremy Ralat, 39Raul Ralat, 36Alison E Ralbovsky, 42Taylor Ralbovsky, 34Debra J Raleeh, 70Andrew B Raleigh, 47Ashley Raleigh, 35Christy E Raleigh, 64

Ryan Rakvic Phones & Addresses

  • 106 Malier Dr, Arnold, MD 21012 (410) 757-4501
  • 50 Harbour Heights Dr, Annapolis, MD 21401 (443) 949-9502
  • New Kensington, PA
  • Palo Alto, CA
  • Santa Clara, CA
  • San Jose, CA
  • Pittsburgh, PA
  • 106 Malier Dr, Arnold, MD 21012

Work

Company: Intel corporation Oct 2000 to Aug 2005 Position: Senior research engineer

Education

Degree: Master of Science, Doctorates, Masters, Doctor of Philosophy School / High School: Carnegie Mellon University 1997 to 2004 Specialities: Computer Engineering

Skills

Computer Architecture • Simulations • Embedded Systems • Matlab • Algorithms • High Performance Computing • C • C++ • Linux • Java • Software Engineering • Latex • Perl • Systems Engineering • Program Management • Computer Engineering • Programming • Operating Systems

Industries

Computer Hardware

Resumes

Resumes

Ryan Rakvic Photo 1

Associate Professor

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Location:
Annapolis, MD
Industry:
Computer Hardware
Work:
Intel Corporation Oct 2000 - Aug 2005
Senior Research Engineer
United States Naval Academy Oct 2000 - Aug 2005
Associate Professor
Education:
Carnegie Mellon University 1997 - 2004
Master of Science, Doctorates, Masters, Doctor of Philosophy, Computer Engineering University of Michigan 1993 - 1997
Bachelors, Bachelor of Science, Computer Engineering
Skills:
Computer Architecture
Simulations
Embedded Systems
Matlab
Algorithms
High Performance Computing
C
C++
Linux
Java
Software Engineering
Latex
Perl
Systems Engineering
Program Management
Computer Engineering
Programming
Operating Systems

Publications

Us Patents

Marking In History Table Instructions Slowable/Delayable For Subsequent Executions When Result Is Not Used Immediately

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US Patent:
6954848, Oct 11, 2005
Filed:
Jan 2, 2002
Appl. No.:
10/038038
Inventors:
Ryan Rakvic - Santa Clara CA, US
Christopher Wilkerson - Portland OR, US
Bryan Black - Austin TX, US
Edward Grochowski - San Jose CA, US
John Shen - San Jose CA, US
Edward Brekelbaum - Austin TX, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F009/30
US Classification:
712214, 712205, 712216
Abstract:
After an instruction loads data into a register at a first time, the register is monitored to see if it is read in a next clock cycle. When the data is not read in the next clock cycle, the instruction is classified as a slowable instruction. An instruction address associated with the instruction is used to update a history table. The history table stores information to indicate if an instruction is a slowable instruction or a non-slowable instruction. When the instruction address of the instruction is encountered at a second time, the history table is used to determine if the instruction is slowable or non-slowable.

Cache Mechanism

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US Patent:
7120749, Oct 10, 2006
Filed:
Mar 18, 2004
Appl. No.:
10/803452
Inventors:
Ryan Rakvic - Palo Alto CA, US
Youfeng Wu - Palo Alto CA, US
Bryan Black - Austin TX, US
John Shen - San Jose CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/12
US Classification:
711133
Abstract:
According to one embodiment a system is disclosed. The system includes a central processing unit (CPU), a first cache memory coupled to the CPU to store only data for vital loads that are to be immediately processed at the CPU, a second cache memory coupled to the CPU to store data for semi-vital loads to be processed at the CPU, and a third cache memory coupled to the CPU, the first cache memory and the second cache memory to store non-vital loads to be processed at the CPU.

Parallel Cachelets

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US Patent:
7216201, May 8, 2007
Filed:
Jan 9, 2006
Appl. No.:
11/327454
Inventors:
Ryan N. Rakvic - Santa Clara CA, US
John P. Shen - San Jose CA, US
Deepak Limaye - Austin TX, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
US Classification:
711118, 711150, 711168, 711210
Abstract:
Parallel cachelets are provided for a level of cache in a microprocessor. The cachelets may be independently addressable. The level of cache may accept multiple load requests in a single cycle and apply each to a respective cachelet. Depending upon the content stored in each cachelet, the cachelet may generate a hit/miss response to the respective load request. Load requests that hit their cachelets may be satisfied therefrom. Load requests that miss their cachelets may be referred to another level of cache.

Predicate Register File Write By An Instruction With A Pending Instruction Having Data Dependency

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US Patent:
7228402, Jun 5, 2007
Filed:
Jan 2, 2002
Appl. No.:
10/037592
Inventors:
Bohuslav Rychlik - Santa Clara CA, US
Ryan N. Rakvic - Santa Clara CA, US
Edward Brekelbaum - Austin TX, US
Bryan Black - Austin TX, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/00
US Classification:
712217
Abstract:
A method to handle data dependencies in a pipelined computer system is disclosed. The method includes allocating a plurality of registers, enabling execution of computer instructions concurrently by using the plurality of registers, and tracking and reducing data dependencies in the computer instructions by correlating a busy condition of a computer instruction to each register.

Parallel Cachelets

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US Patent:
7424576, Sep 9, 2008
Filed:
Jun 27, 2001
Appl. No.:
09/891523
Inventors:
Ryan N. Rakvic - Santa Clara CA, US
John P. Shen - San Jose CA, US
Deepak Limaye - Austin TX, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
US Classification:
711118, 711150, 711168, 711210
Abstract:
Parallel cachelets are provided for a level of cache in a microprocessor. The cachelets may be independently addressable. The level of cache may accept multiple load requests in a single cycle and apply each to a respective cachelet. Depending upon the content stored in each cachelet, the cachelet may generate a hit/miss response to the respective load request. Load requests that hit their cachelets may be satisfied therefrom. Load requests that miss their cachelets may be referred to another level of cache.

Meeting Point Thread Characterization

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US Patent:
7665000, Feb 16, 2010
Filed:
Mar 7, 2007
Appl. No.:
11/714938
Inventors:
Antonio Gonzalez - Barcelona, ES
Qiong Cai - Barcelona, ES
Jose Gonzalez - Terrassa, ES
Pedro Chaparro - La-Garriga Barcelona, ES
Grigorios Magklis - Barcelona, ES
Ryan Rakvic - Annapolis MD, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G01R 31/28
US Classification:
714724, 709107
Abstract:
An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic to periodically identify which thread in a set of threads is a critical thread. The critical thread may be the slowest thread and criticality may be determined by examining meeting point counts. The embodiment may also include logic to selectively manipulate a configurable attribute of the critical thread and/or core upon which the critical thread will run.

Sequencer Address Management

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US Patent:
7743233, Jun 22, 2010
Filed:
Apr 5, 2005
Appl. No.:
11/100032
Inventors:
Hong Wang - Fremont CA, US
Gautham N. Chinya - Hillsboro OR, US
Richard A. Hankins - San Jose CA, US
Shivnandan D. Kaushik - Portland OR, US
Bryant Bigbee - Scottsdale AZ, US
John Shen - San Jose CA, US
Per Hammarlund - Hillsboro OR, US
Xiang Zou - Beaverton OR, US
Jason W. Brandt - Austin TX, US
Prashant Sethi - Folsom CA, US
Douglas M. Carmean - Beaverton OR, US
Baiju V. Patel - Portland OR, US
Scott Dion Rodgers - Hillsboro OR, US
Ryan N. Rakvic - Palo Alto CA, US
John L. Reid - Portland OR, US
David K. Poulsen - Champaign IL, US
Sanjiv M. Shah - Champaign IL, US
James Paul Held - Portland OR, US
James Charles Abel - Phoenix AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/00
US Classification:
712220
Abstract:
Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

Mechanism For Monitoring Instruction Set Based Thread Execution On A Plurality Of Instruction Sequencers

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US Patent:
8010969, Aug 30, 2011
Filed:
Jun 13, 2005
Appl. No.:
11/151809
Inventors:
Richard A. Hankins - San Jose CA, US
Gautham N. Chinya - Hillsboro OR, US
Hong Wang - Fremont CA, US
Shivnandan D. Kaushik - Portland OR, US
Bryant E. Bigbee - Scottsdale AZ, US
John P. Shen - San Jose CA, US
Trung A. Diep - San Jose CA, US
Xiang Zou - Beaverton OR, US
Baiju V. Patel - Portland OR, US
Paul M. Petersen - Champaign IL, US
Sanjiv M. Shah - Champaign IL, US
Ryan N. Rakvic - Palo Alto CA, US
Prashant Sethi - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 3/00
G06F 9/46
G06F 7/38
US Classification:
719318, 718100, 712235
Abstract:
A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.
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Ryan N Rakvic from Arnold, MD, age ~49 Get Report