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Ryan E Feemster

from Austin, TX
Age ~63
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Also known as:
Ryan Ervin Feemster, Ryan Seemster, Ryan Austin
Phone and address:
2930 Kassarine Pass, Austin, TX 78704
Related to:
Clinton Mylo FeemsterManjit BhattiSharon K Bhatti, 46Colleen Cruze, 37Colleen BhattiRobert Guerra, 47
Connected to:
Bryan D Feemster, 48Eboni Feemster, 42Georgia S Feemster, 79Martin C Feemster, 42Sarah J Feemster, 46Dennis M Feenaghty, 53Judy E Feener, 70Alan Feeney, 65Alena O Feeney, 55Brianna Feeney, 31

Ryan Feemster Phones & Addresses

  • 2930 Kassarine Pass, Austin, TX 78704
  • Horseshoe Bay, TX
  • Sugar Land, TX
  • Raleigh, NC
  • Nashville, TN

Work

Company: Microsemi corporation Position: Technical fellow

Education

Degree: Bachelor's degree or higher

Resumes

Resumes

Ryan Feemster Photo 1

Technical Fellow

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Location:
Austin, TX
Work:
Microsemi Corporation
Technical Fellow

Publications

Us Patents

Synchronizing Circuit Of Two Clock Signals

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US Patent:
50862367, Feb 4, 1992
Filed:
Aug 27, 1990
Appl. No.:
7/572716
Inventors:
Ryan E. Feemster - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H03K 513
H03K 19096
US Classification:
307269
Abstract:
There is disclosed a synchronizing circuit for synchronizing a first clock signal to a second clock signal. The synchronizing circuit includes an edge-triggered set-reset latch and a delay circuit. A subclock generator generates first and second subclock signals from a synchronizing clock to control the delay circuit so that the synchronized signal at the output of the circuit is exactly one full cycle period of the synchronizing clock signal.

Interrupt Vector Method And Apparatus For Loading A Slot Memory Address Counter

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US Patent:
56780486, Oct 14, 1997
Filed:
May 4, 1995
Appl. No.:
8/433757
Inventors:
Brett Stewart - Austin TX
Ryan Feemster - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 946
US Classification:
395739
Abstract:
An interrupt vector approach for a processor system loads an interrupt vector directly into an address. register to minimize overhead of processing interrupts. A plurality of interrupt triggers correspond to a plurality of interrupt vector registers, each containing a programmable interrupt vector. Upon activation of one of the interrupt triggers, the contents of the corresponding interrupt vector is loaded into a slot memory address counter. The address counter addresses a sequencer slot memory which contains the starting addresses of sequences of instructions stored in an instruction memory. An instruction address counter receives addresses from the sequencer slot memory and provides addresses to the instruction memory. Upon activation of said one of the interrupt triggers, execution of one of the sequences beginning at the address contained in the interrupt register corresponding to the active interrupt trigger is begun, and addresses of the sequences in sequencer slot memory are sequentially loaded into the instruction address counter until a stop bit is indicated in a word in the sequencer slot memory.

Interrupt Vector Method And Apparatus

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US Patent:
55577644, Sep 17, 1996
Filed:
May 4, 1995
Appl. No.:
8/433758
Inventors:
Brett Stewart - Austin TX
Ryan Feemster - Austin TX
Assignee:
Advanced Micro Devices Inc. - Sunnyvale CA
International Classification:
G06F 946
US Classification:
395375
Abstract:
An interrupt vector approach for a processor system loads an interrupt vector directly into an address register to minimize overhead of processing interrupts. A plurality of interrupt triggers correspond to a plurality of interrupt vector registers, each containing a programmable interrupt vector. Upon activation of one of the interrupt triggers, the contents of the corresponding interrupt vector is loaded into a slot memory address counter. The address counter addresses a sequencer slot memory which contains the starting addresses of sequences of instructions stored in an instruction memory. An instruction address counter receives addresses from the sequencer slot memory and provides addresses to the instruction memory. Upon activation of said one of the interrupt triggers, execution of one of the sequences beginning at the address contained in the interrupt register corresponding to the active interrupt trigger is begun, and addresses of the sequences in sequencer slot memory are sequentially loaded into the instruction address counter until a stop bit is indicated in a word in the sequencer slot memory.

Charge Dissipation In Capacitively Loaded Ports

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US Patent:
55460399, Aug 13, 1996
Filed:
Apr 17, 1995
Appl. No.:
8/423059
Inventors:
Larry D. Hewitt - Austin TX
Ryan Feemster - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H03K 1716
H03K 512
US Classification:
327379
Abstract:
A cascade of triggering circuits sequentially activates a series of parallel pull-down paths in reflexive response to a pull-down signal indicating correspondence between the potential on a capacitively loaded port and a selectable threshold voltage. The triggering circuits are clocked with a common signal to sequentially propagate the pull-down signal from prior to subsequent triggering stages to sequentially activate corresponding parallel paths. In a preferred embodiment, the D flip-flops of a sequential cascade control multiple pull-down paths to regulate charging and discharging of a joystick capacitive load on a monolithic audio personal computer IC game port. To initiate charging of the joystick capacitor, the flip-flops simultaneously disable the pull-down paths in response to a system WRITE signal. To discharge the joystick capacitor, the flip-flops sequentially propagate a comparator derived pull-down signal to sequentially enable the pull-down paths to controllably dissipate the accumulated charge.

Monolithic Pc Audio Circuit With Enhanced Digital Wavetable Audio Synthesizer

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US Patent:
56594666, Aug 19, 1997
Filed:
Nov 2, 1994
Appl. No.:
8/333536
Inventors:
David Norris - Austin TX
Jeffrey M. Blumenthal - Austin TX
Geoffrey E. Brehmer - Lexington TX
Glen W. Brown - Austin TX
Carlin Dru Cabler - Austin TX
Ryan Feemster - Austin TX
David Guercio - Austin TX
Dale E. Gulick - Austin TX
Larry D. Hewitt - Austin TX
Michael Hogan - Austin TX
Alfredo R. Linz - Austin TX
Paul G. Schnizlein - Austin TX
Martin P. Soques - Austin TX
Michael E. Spak - Kyle TX
David N. Suggs - Austin TX
Alan T. Torok - Pflugerville TX
Assignee:
Advanced Micro Devices, Inc. - Austin TX
International Classification:
G06F 316
US Classification:
36440001
Abstract:
A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44. 1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field.

Device And Method For Interprocessor Communication Using Mailboxes Owned By Processor Devices

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US Patent:
56088736, Mar 4, 1997
Filed:
Jul 3, 1996
Appl. No.:
8/675217
Inventors:
Ryan Feemster - Austin TX
David Dettmer - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 1314
US Classification:
39520008
Abstract:
A device and method for providing inter-processor communication in a multi-processor architecture. A post office RAM has a plurality of mailboxes. Each mailbox is write-accessible by one port, but is read-accessible by the other ports. Thus, a processor device on a port has write-access to one mailbox, but can read the other mailboxes in the post office. A transmitting processor communicates with a receiving processor, by utilizing the post office. The transmitting processor writes information into its own mailbox, and signals a receiving processor. The receiving processor determines which of the processor devices signalled it, and reads the information in the transmitting processor's mailbox.

Interrupt Vector Method And Apparatus

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US Patent:
54737630, Dec 5, 1995
Filed:
Aug 2, 1993
Appl. No.:
8/100152
Inventors:
Brett Stewart - Austin TX
Ryan Feemster - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F 946
US Classification:
395375
Abstract:
An interrupt vector approach for a processor system loads an interrupt vector directly into an address register to minimize overhead of processing interrupts. A plurality of interrupt triggers correspond to a plurality of interrupt vector registers, each containing a programmable interrupt vector. Upon activation of one of the interrupt triggers, the contents of the corresponding interrupt vector is loaded into a slot memory address counter. The address counter addresses a sequencer slot memory which contains the starting addresses of sequences of instructions stored in an instruction memory. An instruction address counter receives addresses from the sequencer slot memory and provides addresses to the instruction memory. Upon activation of said one of the interrupt triggers, execution of one of the sequences beginning at the address contained in the interrupt register corresponding to the active interrupt trigger is begun, and addresses of the sequences in sequencer slot memory are sequentially loaded into the instruction address counter until a stop bit is indicated in a word in the sequencer slot memory.

Comparator Circuit

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US Patent:
52870154, Feb 15, 1994
Filed:
Jan 22, 1992
Appl. No.:
7/824029
Inventors:
Miki Z. Moyal - Austin TX
Ryan E. Feemster - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H03K 524
H03K 1716
US Classification:
307355
Abstract:
An apparatus is disclosed for comparing a first input signal with a second input signal and generating an output signal representative of that comparison in response to a system clock signal. The apparatus comprises a plurality of amplifying circuits. A first amplifying circuit generates a pair of first amplifier signals representative of the input signals applied to the apparatus. A second amplifying circuit receives the pair of first amplifier signals and generates a pair of second amplifier signals representative of the pair of first amplifier signals. A delay circuit receives the system clock signal and generates a delayed clock signal which follows the system clock signal by predetermined interval. A first switching circuit is operatively connected across the first amplifier outputs and responds to the system clock signal. A second switching circuit is operatively connected across the second amplifier outputs and is responsive to the delayed clock signal.
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Ryan E Feemster from Austin, TX, age ~63 Get Report