Russell R Fling

46022767, Jul 22, 1986

Apr 12, 1984

6/599531

Russell T. Fling - Noblesville IN
Donald H. Willis - Indianapolis IN
David L. McNeely - Indianapolis IN

RCA Corporation - Princeton NJ

H04N 968

358 27

A signal overload circuit for use in e. g. a digital TV receiver includes a piecewise linear weighting circuit which weights samples of greater magnitude proportionately more heavily than samples of lesser magnitude. The weighted samples are applied to an accumulator, and the accumulated value over a field interval is compared to an overload reference value to generate an overload output signal which is combined with other gain factors for application as the common gain control signal to a common amplifier. The overload detector is coupled in a feedback loop around the common amplifier. In order not to defeat the function of the other gain factors, the overload detector is programmable and its sensitivity is made responsive to the other gain factors.

48643998, Sep 5, 1989

Mar 31, 1987

7/032258

Eric D. Romesburg - Indianapolis IN
Russell T. Fling - Noblesville IN

RCA Licensing Corporation - Princeton NY

H04N 504

358148

A digital TV receiver includes an apparatus for generating a skew corrected clock. The apparatus consists of a fixed frequency, free running oscillator for producing a signal having a frequency which is a fixed integer multiple K of the desired nominal frequency of the skew-corrected clock signal, and a divide-by-K circuit which is reset once every horizontal line. In accordance with another aspect of this invention, the state of the divide-by-K circuit is captured and saved for use in a chroma demodulation apparatus just before it is reset.

50635808, Nov 5, 1991

May 7, 1990

7/520204

Barth A. Canfield - Indianapolis IN
Russell T. Fling - Naperville IL

Thomson Consumer Electronics, Inc. - Indianapolis IN

H03K 2102

377 55

Apparatus for controlling the time constant of a signal includes an up/down counter for counting pulses of a clock signal. The count value is utilized as output signal. The output signal is compared with the input signal to provide a first control signal determinative of whether the counter counts up or down. The output signal is compared with the input signal offset by a constant value to provide a signal which is ORed with the first control signal, and the ORed signal is utilized to enable/disable the counter. Applying a constant offset value to the input signal to be compared precludes the system from alternately counting up and down by one unit value during intervals of relatively constant amplitude input signals.

45503397, Oct 29, 1985

Nov 21, 1983

6/554082

Russell T. Fling - Noblesville IN

RCA Corporation - Princeton NJ

H04N 9535

358 28

A pipelined binary divider which operates at video rates which consists of N like subtraction stages coupled in cascade. Each subtraction stage includes a latch for storing the divisor, the partial quotient and a modified dividend from the previous stage. A binary multiplier is arranged to multiply the latched modified dividend by a factor of two, the result being applied as the minuend to a binary subtractor and to one input of a multiplexer. The latched divisor is applied as the subtrahend to the subtraction circuit. The sign bit from the subtraction circuit controls the multiplexer to selectively pass the multiplied dividend as the dividend to the succeeding stage, for negative differences, or the magnitude of the difference from the subtraction circuit for positive differences. The sign bit is complemented and applied as an additional least significant bit (LSB) to the partial quotient. Each stage adds one bit to the quotient.

46565167, Apr 7, 1987

Mar 25, 1985

6/715263

Russell T. Fling - Noblesville IN
Todd J. Christopher - Indianapolis IN

RCA Corporation - Princeton NJ

H04N 5272

358183

A pix-in-pix television display includes a memory for holding samples representing one field of the small picture. Samples which are to be written into the memory are developed in a buffer memory one line at a time over intervals corresponding to the three line periods of the signal which produces the small picture. A line of samples is written from the buffer memory into the field memory over three line periods of the small picture signal. The memory write operation is suspended when data is read from the field memory for display. The write operation resumes when a read operation is completed at the address and pixel value which were being written when the write operation was suspended.

45890846, May 13, 1986

May 16, 1983

6/495116

Russell T. Fling - Noblesville IN
Saiprasad V. Naimpally - Indianapolis IN

RCA Corporation - Princeton NJ

G06F 738
H04N 964

364745

Symmetrical truncation of two's complement binary numbers is performed by simply discarding the LSB's of positive values and by adding "one" to the truncated negative value when any one of the discarded LSB's is a logical "one" value. Apparatus to perform an N bit truncation includes an incrementer, a two input AND gate and an N-input OR gate.

46059628, Aug 12, 1986

Nov 30, 1984

6/676946

Todd J. Christopher - Indianapolis IN
Russell T. Fling - Fishers IN

RCA Corporation - Princeton NJ

H04N 701

358140

A television receiver/monitor includes a progressive scan processor including memories for time compressing a video input signal and doubling the line rate to reduce visible line structure when the double line-rate signal is displayed. The memories are controlled to provide a video compression factor (2. 5:1) greater than the display line rate increase (2:1) to provide a display retrace time (10. 8 micro-seconds) substantially equal to the blanking interval (11. 0 micro-seconds) of the video input signal thereby decreasing display power losses and horizontal drive requirements.

46397639, Jan 27, 1987

Apr 30, 1985

6/729014

Donald H. Willis - Marion County IN
Russell T. Fling - Fishers IN

RCA Corporation - Princeton NJ

H04N 977

358 11

A speed-up memory converts interlaced RGB input signals to double line-rate (progressive scan) form. A vertical detail signal is derived from the RGB input signals before or after speed-up and a vertical peaking signal is derived from the detail signal. During the first read operation of the speed-up memory both signals are added to the speeded-up signals to effect a preshoot of the resultant signal and during the second speed-up memory read operation only the peaking signal added to affect an overshoot of the resultant signals whereby alternate lines of the converted RGB signals exhibit enhanced vertical detail.