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Ruoping Wang Phones & Addresses

  • Fishkill, NY
  • 9013 Sommerland Way, Austin, TX 78749 (512) 301-3809
  • University Park, PA
  • Provo, UT
  • Fullerton, CA
  • 9013 Sommerland Way, Austin, TX 78749 (512) 760-5043

Work

Company: Austin texas area Position: Ustc

Education

Degree: High school graduate or higher

Skills

Semiconductors

Emails

Industries

Semiconductors

Resumes

Resumes

Ruoping Wang Photo 1

Ustc

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Austin Texas Area
Ustc
Skills:
Semiconductors

Business Records

Name / Title
Company / Classification
Phones & Addresses
Ruoping Wang
Director
QUANTUM RESEARCH GROUP, INC
108 Billings Ln, Austin, TX 78733

Publications

Us Patents

Method And Apparatus For Making An Integrated Circuit Using Polarization Properties Of Light

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US Patent:
6645678, Nov 11, 2003
Filed:
Dec 1, 2000
Appl. No.:
09/727666
Inventors:
Ruoping Wang - Austin TX
Warren D. Grobman - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G03F 900
US Classification:
430 5
Abstract:
A method and apparatus for making an integrated circuit takes advantage of both polarized and phase shifted light in order to achieve a fine feature. The feature on the integrated circuit is obtained by exposing a first region to light that has a first polarization state, exposing a second portion of the wafer to polarized light in the first polarization state but which is also phase shifted about 180 degrees. A region between the first and second region may be unexposed to light. The region between the first and the second region is the position of the fine feature. In areas where the first region and the second region need to be joined together but no feature is intended to be formed, there is a third region between the first and second regions which is exposed to polarized light that has a second polarization state which is orthogonal to that of the polarized light which exposes the first and second regions. The result is that the boundary between either the first or second region and the third region is fully exposed. Thus there is no artifact or extra feature formed in this boundary area between the first and second regions.

Method And Apparatus For Forming A Pattern On An Integrated Circuit Using Differing Exposure Characteristics

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US Patent:
20020197541, Dec 26, 2002
Filed:
Jun 20, 2001
Appl. No.:
09/885575
Inventors:
Warren Grobman - Austin TX, US
Ruoping Wang - Austin TX, US
Alfred Reich - Austin TX, US
International Classification:
G03F009/00
G03G016/00
G03C005/00
US Classification:
430/005000, 430/322000
Abstract:
A method of patterning a wafer using four areas with differing exposure characteristics is disclosed. Two areas are phase shifted relative to the other two areas in order to create unexposed areas on the integrated circuit. Two different areas have polarizations orthogonal to each other, are frequency shifted relative to the two other areas, or are exposed by light at a time different than the two other areas to form exposed areas on the integrated circuit. The exposed areas are subsequently removed from the integrated circuit. In one embodiment, the four areas are on the same mask. The use of four areas with differing exposure characteristics allows for the patterning of more complicated and smaller geometric patterns on the integrated circuit than traditional patterning methods.
Ruoping Wang from Fishkill, NY, age ~83 Get Report