Roxanna Ganji Phones & Addresses
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982 Scorpion Pl, Fremont, CA 94539
Publications
Us Patents
Off-Load Engine To Re-Sequence Data Packets Within Host Memory
View pageUS Patent:
20070081538, Apr 12, 2007
Filed:
Oct 12, 2005
Appl. No.:
11/249690
Inventors:
Roxanna Ganji - Fremont CA, US
International Classification:
H04L 12/56
H04L 12/54
H04L 12/54
US Classification:
370394000, 370428000
Abstract:
A re-sequencing system offloads the cycle intensive task of re-sequencing TCP packets from host memory using a partial offload engine to re-sequence out-of-sequence data packets. However, as opposed to re-ordering the actual data packets, no actual data copy is needed. Instead, packet descriptors associated with each data packet are generated, and it is the packet descriptors that are re-sequenced. The data packets themselves are temporarily stored in packet buffers while the packet descriptors are sorted into sequence. The re-sequencing system preferably re-sequences a data stream of TCP data packets received from an ethernet network. The re-sequencing system is implemented within a computing device, preferably a personal computer or a server.
Reconfigurable Control Processor For Multi-Protocol Resilient Packet Ring Processor
View pageUS Patent:
20030177258, Sep 18, 2003
Filed:
Jan 15, 2003
Appl. No.:
10/346035
Inventors:
Paritosh Kulkarni - San Jose CA, US
Roxanna Ganji - Fremont CA, US
Nirmal Saxena - Los Altos Hills CA, US
Roxanna Ganji - Fremont CA, US
Nirmal Saxena - Los Altos Hills CA, US
Assignee:
Chip Engines - Santa Clara CA
International Classification:
G06F015/173
US Classification:
709/236000, 709/237000, 709/238000, 709/224000
Abstract:
A method and system for adaptive multi-protocol resilient packet ring (RPR) processing are provided. The present invention provides optimal handling operations targeted for both legacy and evolving RPR functions related to topology discovery, fairness algorithms, and control-packet manipulation. Further, the present invention utilizes out-band paths, unique data and instruction memory constructs, and pipeline and multi-thread features to provide wire-rate performance. In one embodiment, a system of the present invention includes instruction memory; a fetch unit associated with instruction memory; a decode unit associated with the fetch unit; at least one execution unit associated with the decode unit; a load/store unit associated with the at least one execution unit; and data memory associated with the load/store unit.