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Ross W Keesler

from Endicott, NY
Age ~68
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Also known as:
Ross Janet Keesler, Ross M Keesler, Ross Kessler
Phone and address:
8 Mansfield Dr, Endicott, NY 13760
(607) 785-0049
Related to:
Adrian Sanchez, 49Sarah Keesler, 41Melissa Keesler, 34Elizabeth Keesler, 38Janet Keesler, 67
Connected to:
Ann M Keesler, 66Candace M Keesler, 51Chris T Keesler, 54Clare R Keesler, 85Daren H Keesler, 63Dorothy L Keesler, 72Jesse A Keesler, 35Linda R Keesler, 73Merle Keesler, 100Michael A Keesler, 74

Ross Keesler Phones & Addresses

  • 8 Mansfield Dr, Endicott, NY 13760 (607) 785-0049
  • Owego, NY
  • 8 Mansfield Dr, Endicott, NY 13760 (607) 341-5945

Work

Company: Endicott interconnect technologies, inc. Position: Product engineer

Education

School / High School: Cornell University

Industries

Electrical/Electronic Manufacturing

Resumes

Resumes

Ross Keesler Photo 1

Product Engineer

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Location:
8 Mansfield Dr, Endicott, NY 13760
Industry:
Electrical/Electronic Manufacturing
Work:
Endicott Interconnect Technologies, Inc.
Product Engineer
Education:
Cornell University

Publications

Us Patents

Composite Laminate Circuit Structure And Method Of Forming The Same

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US Patent:
6451509, Sep 17, 2002
Filed:
Jan 2, 2001
Appl. No.:
09/753015
Inventors:
Ross W. Keesler - Endicott NY
Voya R. Markovich - Endwell NY
Jim P. Paoletti - Endwell NY
Marybeth Perrino - Apalachin NY
William E. Wilson - Waverly NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H05K 111
US Classification:
430311, 430313, 430317, 427 96, 216 13, 361704, 174261, 174262
Abstract:
A method forming a composite laminate structure includes providing first and second circuit board element each having circuitry on at least one face thereof and plated through holes. A voltage plane element is provided having at least one voltage plane having opposite faces with layers of partially cured photodielectric material on each face. At least one hole is photopatterned and etched through the voltage plane element but completely isolated from the voltage plane. Each through hole in the voltage plane element is aligned with a plated through hole in each of the circuit board elements to provide a surface on the voltage plane element communicating with the plated through holes. The voltage plane is laminated between the circuit board elements and the photoimageable material on the voltage plane is fully cured. The surfaces of the voltage plane element communicating with the plated through holes in the circuit board elements are plated with a conducting material to establish a connection between the circuitry on the first and second circuit board elements.

Laminate Having Plated Microvia Interconnects And Method For Forming The Same

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US Patent:
6492600, Dec 10, 2002
Filed:
Jun 28, 1999
Appl. No.:
09/340758
Inventors:
Miguel A. Jimarez - Newark Valley NY
Ross W. Keesler - Owego NY
Voya R. Markovich - Endwell NY
Rajinder S. Rai - Johnson City NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H05K 109
US Classification:
174262, 174256, 174257, 174258, 174263, 174264, 174266, 257698, 257701, 257702, 257737, 257774
Abstract:
A chip carrier structure and method for forming the same having a receptor pad formed therein. The structure comprises a circuitized substrate having a conductive element on the surface, an External Dielectric Layer mounted on the circuitized substrate with an opening positioned above the conductive element to form a microvia. The walls of the microvia are first treated to enhance copper adhesion and then are electroplated to provide a receptor pad. Finally, a solder paste is deposited within the microvia to create a solder deposit or bump.

Through Hole In A Photoimageable Dielectric Structure With Wired And Uncured Dielectric

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US Patent:
6521844, Feb 18, 2003
Filed:
Oct 29, 1999
Appl. No.:
09/430076
Inventors:
Stephen J. Fuerniss - late of Endicott NY
Gary Johansson - Hockessin DE
Ross W. Keesler - Endicott NY
John M. Lauffer - Waverly NY
Voya R. Markovich - Endwell NY
Peter A. Moschak - Whitney Point NY
David J. Russell - Apalachin NY
William E. Wilson - Waverly NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H05K 100
US Classification:
174258, 174262, 174264, 174266
Abstract:
An electronic structure. The electronic structure comprises a layer. The layer includes: a cylindrical volume; a fully cured annular volume of a photoimageable dielectric (PID) material circumscribing the cylindrical volume; and a partially cured remaining volume of the PID material circumscribing the annular volume. The cylindrical volume may include a via. The structure can include a power plane.

High Density Design For Organic Chip Carriers

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US Patent:
6538213, Mar 25, 2003
Filed:
Feb 18, 2000
Appl. No.:
09/506951
Inventors:
Timothy F. Carden - Vestal NY
Todd W. Davies - Vestal NY
Ross W. Keesler - Endicott NY
Robert D. Sebesta - Endicott NY
David B. Stone - Burlington VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01R 1204
US Classification:
174262, 174260
Abstract:
An organic integrated circuit chip carrier for high density integrated circuit chip attach, wherein the contact pads or microvias which provide electrical interconnections to external circuitry are located in a first array pattern, while the plated through holes or through-vias are located in a second array pattern. This allows utilization of wiring channels within the chip carrier in which signal wiring traces can be routed.

Manufacturing Methods For Printed Circuit Boards

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US Patent:
6684497, Feb 3, 2004
Filed:
Feb 20, 2001
Appl. No.:
09/789156
Inventors:
Bernd Karl-Heinz Appelt - Apalachin NY
James Russell Bupp - Endwell NY
Donald Seton Farquhar - Endicott NY
Ross William Keesler - Endicott NY
Michael Joseph Klodowski - Endicott NY
Andrew Michael Seman - Kirkwood NY
Gary Lee Schild - Endicott NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01K 310
US Classification:
29852, 29830, 29831, 29841, 29846
Abstract:
A method of forming a printed circuit board comprising a plurality of conductive bumps with substantially coplanar upper surfaces. The method comprises the steps of applying a metal layer onto a dielectric substrate; applying a first photoresist onto said substrate and exposing and developing said first photoresist to define a pattern of conductive bumps; etching the metal layer exposed by said development to form said plurality of conductive bumps; removing said first photoresist; applying a second photoresist onto the metal layer; exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The present invention is also provides a method for preparing a reinforced panel.

Process Of Fabricating A Circuitized Structure

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US Patent:
6739048, May 25, 2004
Filed:
Jan 27, 2000
Appl. No.:
09/491755
Inventors:
Gerald Walter Jones - Apalachin NY
Ross William Keesler - Endicott NY
Voya Rista Markovich - Endwell NY
William John Rudik - Vestal NY
James Warren Wilson - Vestal NY
William Earl Wilson - Waverly NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01K 310
US Classification:
29852, 29846, 29847, 427 97, 427 99, 174262, 361748, 361792, 361795
Abstract:
A process of fabricating a circuitized structure is provided. The process includes the steps of providing an organic substrate having circuitry thereon; applying a dielectric film on the organic substrate; forming microvias in the dielectric film; sputtering a metal seed layer on the dielectric film and the microvias; plating a metallic layer on the metal seed layer; and forming a circuit pattern thereon.

Two Signal One Power Plane Circuit Board

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US Patent:
6750405, Jun 15, 2004
Filed:
Oct 17, 2000
Appl. No.:
09/690485
Inventors:
Kenneth Fallon - Rochester NY
Miguel A. Jimarez - Newark Valley NY
Ross W. Keesler - Endicott NY
John M. Lauffer - Waverly NY
Roy H. Magnuson - Endicott NY
Voya R. Markovich - Endwell NY
Irv Memis - Vestal NY
Jim P. Paoletti - Endwell NY
Marybeth Perrino - Apalachin NY
John A. Welsh - Binghamton NY
William E. Wilson - Waverly NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01R 1204
US Classification:
174262, 174255
Abstract:
A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers.

Forming A Through Hole In A Photoimageable Dielectric Structure

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US Patent:
6830875, Dec 14, 2004
Filed:
Oct 7, 2002
Appl. No.:
10/266020
Inventors:
Stephen J. Fuerniss - late of Endicott NY
Gary Johansson - Hockessin DE
Ross W. Keesler - Endicott NY
John M. Lauffer - Waverly NY
Voya R. Markovich - Endwell NY
Peter A. Moschak - Whitney Point NY
David J. Russell - Apalachin NY
William E. Wilson - Waverly NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G03F 700
US Classification:
430311, 430312, 430315, 174258
Abstract:
A method for forming an electronic structure. Provides is a layer that includes a cylindrical volume of a photoimageable dielectric (PID) material, an annular volume of the PID material circumscribing the cylindrical volume, and a remaining volume of the PID material circumscribing the annular volume. The layer is photolithograhically exposed to radiation. The annular volume is fully cured by the radiation. The remaining volume is partially cured by the remaining volume by said radiation. The method prevents curing of the cylindrical volume, wherein the PID material in the cylindrical volume remains uncured.
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Ross W Keesler from Endicott, NY, age ~68 Get Report