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Ronald J Wozniak

from Califon, NJ
Age ~67
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Also known as:
Ronald James Wozniak, Ronald J North, Ronald Woznaik, Ron Woznik
Phone and address:
50 Fairmount Rd W, Califon, NJ 07830
Related to:
Timothy J Woodard, 56April M Wozniak, 39Michael WozniakSharon L Wozniak, 68Joel W Woodard, 64Olga Kavun, 50Sandra A Woodard, 78Denise P Wozniak, 69Michael J Wozniak, 41Robert P Wozniak, 55Phillip J WozniakAdrienne A Wozniak, 96Susan M North, 64
Connected to:
Alicja J Wozniak, 54Bryan Wozniak, 37Danielle F Wozniak, 65Dawid T Wozniak, 33Denis G Wozniak, 81Diana E Wozniak, 54Doroteya N Wozniak, 41Douglas C Wozniak, 78Glenn G Wozniak, 77Hunter J Wozniak, 28

Ronald Wozniak Phones & Addresses

  • 50 Fairmount Rd W, Califon, NJ 07830
  • 992 Congress St, Whitehall, PA 18052 (610) 437-5005
  • 2447 Howard St, Allentown, PA 18103 (610) 797-9567
  • Macungie, PA
  • Lehighton, PA

Work

Position: Production Occupations

Resumes

Resumes

Ronald Wozniak Photo 1

Principal Engineer

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Location:
50 Fairmount Rd west, Califon, NJ 07830
Industry:
Semiconductors
Work:
Bae Systems
Principal Engineer
Superior Talent Resource Sep 2017 - Dec 2017
Various Consulting Assignments
Microsemi Corporation May 2013 - Jul 2016
Fpga Design and High Speed Digital Asic Design
Esilicon Oct 2011 - May 2013
Senior Memory Design
Lsi Corporation Apr 2007 - Oct 2011
Senior Memory Design
Education:
University of Minnesota 1979 - 1981
Master of Science, Masters, Engineering Saint John's University 1975 - 1979
Bachelors, Bachelor of Arts, Bachelor of Science, Mathematics, Physics Hill - Murray School
St. John's University, Collegeville, Mn
University of Minnesota - Twin Cities
Skills:
Asic
Ic
Cmos
Semiconductors
Eda
Debugging
Fpga
Verilog
Vlsi
Static Timing Analysis
Analog
Vhdl
Embedded Systems
Soc
Rtl Design
Cadence
Circuit Design
Sram
Mixed Signal Ic Design
Rf Design
Digital Circuit Design
High Speed Digital Design
High Speed Interfaces
Electrical Troubleshooting
Physical Design
Spice
Low Power Design
Dft
Bist
Design For Manufacturing
Functional Verification
Timing Closure
Microsoft Office
Microsoft Excel
Shell Scripting
C
Python
Matlab
Originlab
Mathcad
Numerical Analysis
Cadence Virtuoso
Monte Carlo Simulation
Synopsys Tools
Synopsys Primetime
Data Analysis
Data Visualization
Tutoring
Mentoring
Team Building
Interests:
Children
Economic Empowerment
Civil Rights and Social Action
Environment
Education
Science and Technology
Disaster and Humanitarian Relief
Human Rights
Animal Welfare
Arts and Culture
Health
Ronald Wozniak Photo 2

Ronald Wozniak

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Ronald Wozniak Photo 3

Principal Engineer At Lsi Logic

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Position:
Principal Electrical Engineer at LSI Logic, Memory Design at LSI
Location:
Allentown, Pennsylvania Area
Industry:
Semiconductors
Work:
LSI Logic since Aug 1981
Principal Electrical Engineer
LSI since 1981
Memory Design
LSI Corporation 1981 - 2010
DMTS Memory Design Engineer
Ronald Wozniak Photo 4

Dmts At Agere

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Position:
DMTS at Agere, was DMTS at LSI Corporation, DMTS at Agere Systems
Location:
Allentown, Pennsylvania Area
Industry:
Semiconductors
Work:
Agere
DMTS
LSI Corporation since 1981
was DMTS
Agere Systems since 1981
DMTS
Education:
University of Minnesota-Twin Cities 1976 - 1981

Publications

Us Patents

Integrated Circuit Packages

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US Patent:
H73, Jun 3, 1986
Filed:
Aug 25, 1983
Appl. No.:
6/526413
Inventors:
Kenneth K. Claasen - Lower Nazareth Township, Northampton County PA
Ronald N. Graver - Allentown PA
Frank P. Pelletier - Allentown PA
Kurt M. Striny - Emmaus PA
Ronald J. Wozniak - Allentown PA
Assignee:
AT&T Bell Laboratories - Murray Hill NJ
International Classification:
H01L 2328
US Classification:
357 72
Abstract:
A package for wire-bonded semiconductor integrated circuit chips is disclosed. The chip is covered by a protective layer of material such as room temperature vulcanizing silicone rubber. The thickness of the layer is such that it covers a portion of the arched wires, thereby concentrating the stresses away from the wire-ball bond interfaces. The chip is encapsulated in a plastic material while providing an air gap between the plastic and protective layer.

Decoding Techniques For Read-Only Memory

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US Patent:
7301828, Nov 27, 2007
Filed:
Feb 27, 2006
Appl. No.:
11/363366
Inventors:
Dennis E. Dudeck - Hazleton PA, US
Donald A. Evans - Lancaster OH, US
Hai Q. Pham - Hatfield PA, US
Wayne E. Werner - Coopersburg PA, US
Ronald J. Wozniak - Allentown PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G11C 7/00
US Classification:
36518908, 36523002, 365190
Abstract:
A memory circuit includes a number of bit line structures, each including at least three bit lines; a number of word lines that intersect with the bit line structures at a number of sites; and a number of switching devices located at the sites. A number of column sense logic units are also provided, corresponding to the bit line structures. Each of the column sense logic units includes a first logic gate and a second logic gate. The first logic gate has a first input connected with a first one of the bit lines and a second input connected with a second one of the bit lines. The second logic gate has a first input interconnected with a third one of the bit lines, and a second input interconnected with the second one of the bit lines.

Layout Techniques For Memory Circuitry

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US Patent:
7324364, Jan 29, 2008
Filed:
Feb 27, 2006
Appl. No.:
11/363010
Inventors:
Dennis E. Dudeck - Hazleton PA, US
Donald A. Evans - Lancaster OH, US
Hai Q. Pham - Hatfield PA, US
Wayne E. Werner - Coopersburg PA, US
Ronald J. Wozniak - Allentown PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G11C 5/06
US Classification:
365 63, 365 52
Abstract:
An integrated circuit includes memory circuitry with a number of bit line structures, each including at least three bit lines; a number of word lines that intersect with the bit line structures at a number of sites; and a number of switching devices located at the sites. A number of Vplanes are interconnected with the switching devices. The switching devices and the Vplanes are formed at a first level. The Vplanes can be formed as substantially complementary interlocking regions that also form functional portions of the switching devices. The switching devices can be connected between an adjacent one of the word lines and a selected one of the bit lines of an adjacent one of the bit line structures for selective electrical conduction therebetween upon activation by the adjacent one of the word lines.

Accelerated Searching For Content-Addressable Memory

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US Patent:
7391633, Jun 24, 2008
Filed:
Jul 26, 2006
Appl. No.:
11/460045
Inventors:
Dennis E. Dudeck - Hazleton PA, US
Donald Albert Evans - Lancaster OH, US
Hai Quang Pham - Hatfield PA, US
Wayne E. Werner - Coopersburg PA, US
Ronald James Wozniak - Allentown PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G11C 15/00
US Classification:
365 491, 365 4911, 365 4917, 3651852, 365203, 365207, 711108
Abstract:
A sensing circuit for use with a CAM circuit including multiple match lines and multiple CAM cells connected to the match lines includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing circuit. The switching circuit is operative to selectively connect the charge sharing circuit to a corresponding one of the match lines as a function of a first control signal supplied to the switching circuit. The sensing circuit further includes at least one comparator circuit connected to the corresponding match line and operative to generate an output signal indicative of a match between search data supplied to at least a given one of the CAM cells connected to the corresponding match line and data stored in the given CAM cell. The charge sharing circuit is operative to remove an amount of charge on the corresponding match line so as to reduce a voltage on the corresponding match line in conjunction with a search operation of the CAM cell.

Accelerated Single-Ended Sensing For A Memory Circuit

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US Patent:
7433254, Oct 7, 2008
Filed:
Jul 26, 2006
Appl. No.:
11/460035
Inventors:
Dennis E. Dudeck - Hazleton PA, US
Donald Albert Evans - Lancaster PA, US
Hai Quang Pham - Hatfield PA, US
Wayne E. Werner - Coopersburg PA, US
Ronald James Wozniak - Allentown PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G11C 7/02
US Classification:
3652101, 36521012, 365205, 365207, 365196
Abstract:
A single-ended sensing circuit is provided for use with a memory circuit including a plurality of bit lines and a plurality of memory cells connected to the bit lines. The sensing circuit includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing circuit. The switching circuit is operative to selectively connect the charge sharing circuit to at least a given one of the bit lines as a function of a first control signal supplied to the switching circuit. The sensing circuit further includes at least one comparator circuit connected to the given bit line. The comparator circuit is operative to generate an output signal indicative of a logical state of a memory cell connected to the given bit line. The charge sharing circuit is operative to remove an amount of charge on the given bit line so as to reduce a voltage on the given bit line in conjunction with a read access of the memory cell.

Memory Cell For Content-Addressable Memory

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US Patent:
7558095, Jul 7, 2009
Filed:
May 2, 2007
Appl. No.:
11/743163
Inventors:
Dennis E. Dudeck - Hazleton PA, US
Donald Albert Evans - Lancaster OH, US
Hai Quang Pham - Hatfield PA, US
Wayne E. Werner - Coopersburg PA, US
Ronald James Wozniak - Allentown PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G11C 15/00
US Classification:
365 491, 365 4911, 365 4917, 365 4918
Abstract:
A memory cell for use in a content-addressable memory comprises a first latch and a second latch. The first latch is operative to store a first bit associated with a first stored word, while the second latch is operative to store a second bit associated with a second stored word. The first and second latches collectively comprise a plurality of latch transistors. Each of the latch transistors comprises a respective channel. The channels of the latch transistors are oriented in substantially the same direction, resulting in a very compact memory cell implementation.

Reduced Leakage Driver Circuit And Memory Device Employing Same

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US Patent:
7633830, Dec 15, 2009
Filed:
Nov 29, 2007
Appl. No.:
11/947210
Inventors:
Donald Albert Evans - Lancaster OH, US
Richard J. McPartland - Nazareth PA, US
Hai Quang Pham - Hatfield PA, US
Wayne E. Werner - Coopersburg PA, US
Ronald James Wozniak - Allentown PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G11C 8/00
US Classification:
36523006, 36523008, 36523311, 3652331
Abstract:
A row line driver circuit for use in a memory array including multiple memory cells and multiple row lines coupled to the memory cells for selectively accessing the memory cells includes an output stage adapted for connection to a corresponding one of the row lines and a control circuit connected to the output stage. The output stage is operative during an active phase of a given memory cycle to drive the corresponding row line to a potential as a function of at least one address signal received by the driver circuit. The control circuit is operative to generate at least one control signal for disabling the output stage at least during an inactive phase of the memory cycle to thereby substantially eliminate a leakage current path in the driver circuit.

Process And Temperature Tolerant Non-Volatile Memory

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US Patent:
7755948, Jul 13, 2010
Filed:
Aug 19, 2008
Appl. No.:
12/194028
Inventors:
Dennis Dudeck - Hazelton PA, US
Donald Evans - Lancaster OH, US
Hai Pham - Hatfield PA, US
Wayne Werner - Coopersburg PA, US
Ronald Wozniak - Allentown PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G11C 16/06
US Classification:
36518525, 365203
Abstract:
A nonvolatile memory comprising an array of memory cells and sense amplifiers, each sense amplifier using a keeper circuit to provide an amount of current to compensate for bit line leakage current in the memory array. The amount of current from the keeper depends on the temperature of the memory and the speed of the process used to make the memory.
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Ronald J Wozniak from Califon, NJ, age ~67 Get Report