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Ronald W Schrimpf

from Tucson, AZ
Age ~72
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Also known as:
Ronald William Schrimpf, Rw W Schrimpf, Ronald W Schrimph, Ronald W Scheimpf, Aurora Schrimpf, Ronald F
Phone and address:
442 Calle Margarita, Tucson, AZ 85706
(520) 294-9791
Related to:
Rebecca J Hickman, 25Timothy P Boyd, 60Thomas R Boyd, 61James BoydRoberta Boyd, 88Kelly Valdez, 58
Connected to:
Bonnie Schrimpf, 80Catherine A Schrimpf, 72Diana R Schrimpf, 42Dustin H Schrimpsher, 52Ginger Schrimsher, 44Irene T Schrimp, 92Jessica D Schrimpf, 34Joyce M Schrimsher, 79Kathy Schrimpsher, 64Mary J Schrimpf, 63

Ronald Schrimpf Phones & Addresses

  • 442 Calle Margarita, Tucson, AZ 85706 (520) 294-9791
  • 417 Calle Margarita, Tucson, AZ 85706
  • Sabula, IA
  • Douglas, AZ
  • Pima, AZ
  • 442 W Calle Margarita, Tucson, AZ 85706 (520) 705-9937

Resumes

Resumes

Ronald Schrimpf Photo 1

Administrative Support Coordinator

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Location:
Tucson, AZ
Industry:
Hospital & Health Care
Work:
Tucson Medical Center
Administrative Support Coordinator
Ronald Schrimpf Photo 2

Administrative Support Coordinator

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Location:
Tucson, AZ
Industry:
Hospital & Health Care
Work:
Tucson Medical Center
Administrative Support Coordinator
Tmc Healthcare
Administrative Support Coordinator
Ronald Schrimpf Photo 3

Ronald Schrimpf

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Publications

Us Patents

Method And Apparatus For Evaluating Electrostatic Discharge Conditions

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US Patent:
55571956, Sep 17, 1996
Filed:
Nov 15, 1994
Appl. No.:
8/339823
Inventors:
Ronald D. Schrimpf - Tucson AZ
Sungchul Lee - Tucson AZ
Assignee:
QRP, Inc. - Tucson AZ
International Classification:
G01R 3102
G01N 2760
US Classification:
324 72
Abstract:
A system evaluates occurrences of low level electrostatic discharge events in a manufacturing or processing environment or the like by encapsulating each of a plurality of a MOSFETs in a corresponding package having conductive first and second groups of leads coupled to the gate and source and/or drain electrodes of the MOSFET, respectively. The encapsulated MOSFET then is moved through the environment, wherein an electrostatic discharge causes current to flow into the first external electrode, stressing the gate oxide of the MOSFET and producing a permanent low resistance condition therein. The encapsulated MOSFET then is removed from the environment and tested by measuring an electrical parameter indicative of the low resistance condition between the first and second electrodes of the MOSFET. A statistical analysis then is performed on the data obtained by testing all of the MOSFETs to determine how to reduce or avoid ESD in the environment.

Method And Apparatus For Evaluating Electrostatic Discharge Conditions

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US Patent:
53768795, Dec 27, 1994
Filed:
Nov 3, 1992
Appl. No.:
7/971522
Inventors:
Ronald D. Schrimpf - Tucson AZ
Sungchul Lee - Tucson AZ
Assignee:
QRP, Incorporated - Tucson AZ
International Classification:
G01N 2760
G01R 3126
US Classification:
324 72
Abstract:
A system evaluates occurrences of low level electrostatic discharge events in a manufacturing or processing environment or the like by encapsulating each of a plurality of a MOSFETs in a corresponding package having conductive first and second groups of leads coupled to the gate and source and/or drain electrodes of the MOSFET, respectively. The encapsulated MOSFET then is moved through the environment, wherein an electrostatic discharge causes current to flow into the first external electrode, stressing the gate oxide of the MOSFET and producing a permanent low resistance condition therein. The encapsulated MOSFET then is removed from the environment and tested by measuring an electrical parameter indicative of the low resistance condition between the first and second electrodes of the MOSFET. A statistical analysis then is performed on the data obtained by testing all of the MOSFETs to determine how to reduce or avoid ESD in the environment.

Monocrystalline Three-Dimensional Integrated Circuit

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US Patent:
50898620, Feb 18, 1992
Filed:
Nov 30, 1989
Appl. No.:
7/443175
Inventors:
Raymond M. Warner - Edina MN
Ronald D. Schrimpf - Tucson AZ
Alfons Tuszynski - San Diego CA
International Classification:
H01L 2701
H01L 2968
H01L 2978
H01L 2714
US Classification:
357 231
Abstract:
A monocrystalline monolith contains a 3-D array of interconnected lattice-matched devices (which may be of one kind exclusively, or that kind in combination with one or more other kinds) performing digital, analog, image-processing, or neural-network functions, singly or in combination. Localized inclusions of lattice-matched metal and (or) insulator can exist in the monolith, but monolith-wide layers of insulator are avoided. The devices may be self-isolated, junction-isolated, or insulator-isolated, and may include but not be limited to MOSFETs, BJTs, JFETs, MFETs, CCDs, resistors, and capacitors. The monolith is fabricated in a single apparatus using a process such as MBE or sputter epitaxy executed in a continuous or quasicontinuous manner under automatic control, and supplanting hundreds of discrete steps with handling and storage steps interpolated. "Writing" on the growing crystal is done during crystal growth by methods that may include but not be limited to ion beams, laser beams, patterned light exposures, and physical masks. The interior volume of the fabrication apparatus is far cleaner and more highly controlled than that of a clean room.

Method For Fabricating Monolithic And Monocrystalline All-Semiconductor Three-Dimensional Integrated Circuits

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US Patent:
58405895, Nov 24, 1998
Filed:
Jun 6, 1995
Appl. No.:
8/468968
Inventors:
Raymond M. Warner - Edina MN
Ronald D. Schrimpf - Tucson AZ
International Classification:
H01L 21203
US Classification:
437128
Abstract:
A method is described for growing a single crystal having three-dimensional (3-D) doping patterns created within it during growth while maintaining a plane growth surface, creating junction-isolated devices and interconnections, forming a 3-D integrated circuit (IC). The crystal is grown as a large number of lightly-doped layers in a single-pumpdown procedure using sputter epitaxy, which offers growth rates for good-quality silicon of at least 0. 1 micrometer per minute. The process experiences a stable environment with temperature remaining around 400 C and pressure near 1 millitorr, and the process is "quasicontinuous" in that once each layer is in place, its surface will experience a short series of further steps that create a 2-D doping pattern extending through the layer. It is the merging of many such successive 2-D patterns that creates the desired 3-D doping pattern within the finished silicon crystal. Primary layer growth is the first step in a five-step process; second is the growth of a thinner secondary layer of heavily doped silicon to serve as a source of dopant; third is exposing the silicon surface to an intense, patterned, focused light flash from an LCD (or silicon mirror) pattern generator, causing localized dopant diffusion through the primary layer; fourth is the uniform removal by ion milling of a layer thicker than the secondary layer, thus eliminating all dopant from the primary layer except in the selected portions of it affected by the light-induced impurity diffusion; and fifth is a uniform flash annealing of the primary layer.
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Ronald W Schrimpf from Tucson, AZ, age ~72 Get Report