Ronald E Press

7487419, Feb 3, 2009

Dec 16, 2005

11/305849

Nilanjan Mukherjee - Wilsonville OR, US
Jay Jahangiri - Portland OR, US
Ronald Press - Tualatin OR, US

G01R 31/28

714729, 714726, 714727, 714 25, 714 30, 714718, 714724, 714732, 714738, 714739, 714741

Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed test patterns through one or more boundary scan cells. For instance, in one exemplary nonlimiting embodiment, a circuit is disclosed comprising one or more boundary scan cells coupled to primary input ports or primary output ports of a circuit-under-test. The circuit further includes a boundary scan cell controller configured to apply test control signals to the one or more boundary scan cells. In this embodiment, the controller is configured to operate in a mode of operation whereby the controller applies test control signals to the one or more boundary scan cells that correspond to test control signals used to control one or more internal scan chains of the circuit-under-test during testing. The control signals of this exemplary embodiment include an at-speed-clock signal generated outside of the boundary scan cell controller.

6452426, Sep 17, 2002

Apr 16, 2001

09/836700

Nagesh Tamarapalli - Wilsonville OR, 97070
Ronald Press - Tualatin OR, 97062

H03K 1700

327 99, 327166, 327176, 327199, 327294, 327298

A circuit to synchronously select one of the multiple clocks is presented. In one embodiment the selection circuit consists of four main blocks. These are the stable selects block, the decoder block, the synchronous selects block, and the output block. The stable selects block takes select signals as inputs and outputs a signal indicating whether the selects are stable or not, in addition to producing select signals that are synchronous to the current selected clock. The decoder block, decodes the select signals if they are stable, otherwise it re-circulates the previous values of the decoded clock select signals. The stable decoded select signals are then passed on to the synchronous selects block. This block outputs select signals in synchrony with their respective clocks. The synchronous select signals along with the stable decoded signals are used in the output block along with the clocks themselves to generate the final output clock.