Roland T Knaack

6977539, Dec 20, 2005

Aug 26, 2003

10/648090

Declan McDonagh - Duluth GA, US
Roland Knaack - Suwanee GA, US

Integrated Device Technology, Inc. - Santa Clara CA

G06F001/04

327295, 327237

Clock signal generators include an integrated circuit chip having a PLL-based or DLL-based clock driver therein. The clock driver is configured to support generation of a plurality of clock signals having different frequencies in a range between 1 and 1/N times a frequency of an internal clock signal and full-period programmable skew characteristic, where N is a positive integer greater than one. The clock driver also includes a divide-by-N clock generator that is configured to generate N divide-by-N clock signals that have the same frequency but are phase shifted relative to each other. This clock generator operates in response to a first skew signal having a frequency equal to the frequency of the internal clock signal. A one-of-N select circuit is provided. This select circuit is configured to select one of the N divide-by-N clock signals in response to a time unit position signal.

7079446, Jul 18, 2006

Aug 12, 2004

10/916901

Paul Murtagh - Duluth GA, US
Roland T. Knaack - Duluth GA, US

Integrated Device Technology, Inc. - San Jose CA

G11C 8/00

365233, 365191, 711105, 711167

Fully-buffered dual in-line memory modules (FB-DIMM) include advanced memory buffers (AMBs) having enhanced skew, slew rate and output impedance control. The AMB includes user accessible registers that can be programmed to carefully control the edge placement (or phase) of signals generated from the AMB to multiple DRAMs on the module. This control of edge placement, which may be performed independently for each group of signals: clock (CLK, CLK#), command (RAS, CAS, WE), address (including bank address), data (DQ) and data strobe (DQS), provides 360 degrees of control (or one period). This means that any group of signals can be moved independently by one complete period relatively to any other group.

7082071, Jul 25, 2006

Jun 30, 2004

10/881022

Roland T. Knaack - Duluth GA, US
David Stuart Gibson - Suwanee GA, US
Mario Montana - Los Gatos CA, US
Mario Au - Fremont CA, US
Stewart Speed - Sunnyvale CA, US
Srinivas Satish Babu Bamdhamravuri - Duluth GA, US
Uksong Kang - Duluth GA, US

Integrated Device Technology, Inc. - San Jose CA

G11C 7/00

365221, 365191, 365233

An integrated circuit chip includes a plurality of independent FIFO memory devices that are each configured to support all four combinations of DDR and SDR write modes and DDR and SDR read modes and collectively configured to support all four multiplexer, demultiplexer, broadcast and multi-Q operating modes.

7120075, Oct 10, 2006

Jun 24, 2004

10/876339

David Stuart Gibson - Suwanee GA, US
Roland T. Knaack - Duluth GA, US

Integrated Device Technology, Inc. - San Jose CA

G11C 7/00

365221, 36518901, 36518902, 36523005

An integrated circuit chip includes a plurality of independent FIFO memory devices that are each configured to support all four combinations of DDR and SDR write modes and DDR and SDR read modes and collectively configured to support all four multiplexer, demultiplexer, broadcast and multi-Q operating modes. The multi-Q mode of operation supports write path queue switching that is free of write word fall-through and read path queue switching that is free of read word fall-through. The multi-Q mode also supports write path queue switching on every write cycle in both SDR and DDR write modes and independent read path queue switching on every read cycle in both SDR and DDR read modes.

7196562, Mar 27, 2007

Nov 3, 2004

10/979979

Bradley C. Luis - Duluth GA, US
Roland T. Knaack - Suwanee GA, US
Srinivas S. B. Bamdhamravuri - Duluth GA, US

Integrated Device Technology, Inc. - San Jose CA

H03L 7/06

327156, 327147, 327544, 713323

A packaged integrated circuit device includes a nonvolatile memory device and a programmable clock driver circuit therein. The memory device may be provided as an EEPROM device that is disposed on a first integrated circuit substrate and the programmable clock driver circuit may be disposed on a second integrated circuit substrate. The programmable clock driver circuit includes a control circuit and a clock generator therein. The control circuit is configured to detect an error(s) in configuration data that is used by the programmable clock driver circuit. This configuration data is read from the nonvolatile memory and stored in volatile program registers during program restore operations. The control circuit is further configured to automatically idle the clock generator in response to detecting the error in the configuration data. This automatic idling of the clock generator may include operations to set the clock generator at a default setting (e. g. , minimum frequency), which applies to all output banks of the driver circuit.

6173425, Jan 9, 2001

Apr 15, 1998

9/060478

Roland T. Knaack - Suwanee GA
Bruce Lorenz Chin - Duluth GA

Integrated Device Technology, Inc. - Santa Clara CA

G11C 2900

714718

Methods of testing integrated circuits to include data traversal path identification information include the steps of transferring test data into an integrated circuit containing devices therein and then controlling operation of the integrated circuit so that the test data traverses a first path through the devices. At least a portion of the test data and an identification of at least a first portion of the first path are then retrieved from the integrated circuit. This retrieving step may be preceded by the step of overwriting a first portion of the test data with an identification of a first portion of the first path. In the case of a buffer memory device, an identification (e. g. , address) of a current write register (receiving test data) may be "tagged" to a series of test words written into the current write register during test mode operation. Similarly, when the test data is ultimately read from the buffer memory device, an identification of a current read register may be "tagged" to the series of test words being read from the current read register.

20200117629, Apr 16, 2020

Dec 16, 2019

16/715109

- San Jose CA, US
Craig DeSimone - Dacula GA, US
Garret Davey - Cumming GA, US
Yue Yu - Johns Creek GA, US
Roland Knaack - Suwanee GA, US
Scott Herrington - Suwanee GA, US

G06F 13/40
G06F 13/42
G11C 7/10
G11C 11/4096
G11C 7/22
G06F 13/16
G11C 5/04
G11C 11/4076
G11C 11/4093

An apparatus includes a control circuit comprising (i) a first differential data strobe input/output circuit having a first set of driver and termination control inputs and (ii) a second differential data strobe input/output circuit having a second set of driver and termination control inputs. The first and the second sets of driver and termination control inputs are independently programmable. The first and the second differential data strobe input/output circuits operate in a first mode when the first differential data strobe input/output circuit is connected to a first memory device having a first data width and the second differential data strobe input/output circuit is connected to a second memory device having the first data width. The first and the second differential data strobe input/output circuits operate in a second mode when the first differential data strobe input/output circuit and the second differential data strobe input/output circuit are connected in parallel to a single memory device having a second data width.

20190129879, May 2, 2019

Aug 9, 2018

16/059287

- San Jose CA, US
Craig DeSimone - Dacula GA, US
Garret Davey - Cumming GA, US
Yue Yu - Johns Creek GA, US
Roland Knaack - Suwanee GA, US
Scott Herrington - Suwanee GA, US

G06F 13/40
G06F 13/42
G06F 13/16
G11C 11/4096
G11C 7/10
G11C 7/22

An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to operate with the memory devices having a first data width in a first mode and with the memory devices having a second data width in a second mode. The control circuit may be configured to implement two differential data strobe input/output circuits. The differential data strobe input/output circuits each may have driver and termination control inputs that are independently programmable. The differential data strobe input/output circuits may be configured to be connected in parallel when the control circuit is operating in the second mode.