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Robin L Jigour

from El Dorado Hills, CA
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Also known as:
Robin J Jigour, Robin Lynn Jigour
Phone and address:
2670 Cobble Rock Way, Folsom, CA 95762
(916) 358-9800
Connected to:
Robert C Jiguere, 99Jefferson Jih, 71Ming H Jih, 56Victor Jih, 35Anita L Jiha, 59Khalid Jihad, 58Levon S Jihanian, 47Vahe M Jihanian, 90Nicole M Jiho, 43Honey Jijo, 54

Robin Jigour Phones & Addresses

  • 2670 Cobble Rock Way, El Dorado Hls, CA 95762 (916) 358-9800
  • El Dorado Hills, CA
  • 1435 Ranch Ct, San Jose, CA 95132
  • Ranch Ct, San Jose, CA 95132
  • 1435 Ranch Ct, San Jose, CA 95132 (408) 836-0744

Work

Company: Winbond Position: Vice president marketing

Education

Degree: High school graduate or higher

Industries

Semiconductors

Resumes

Resumes

Robin Jigour Photo 1

Vice President Marketing

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Location:
San Jose, CA
Industry:
Semiconductors
Work:
Winbond
Vice President Marketing

Business Records

Name / Title
Company / Classification
Phones & Addresses
Robin J Jigour
Flash Memo
SPANSION LLC
198 Champion Ct, San Jose, CA 95134
915 Devuigne Dr Ms 252, Sunnyvale, CA 94088

Publications

Us Patents

Serial Flash Semiconductor Memory

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US Patent:
7558900, Jul 7, 2009
Filed:
Mar 11, 2005
Appl. No.:
11/078205
Inventors:
Robin J. Jigour - San Jose CA, US
Eungjoon Park - Fremont CA, US
Joo Weon Park - Pleasanton CA, US
Jong Seuk Lee - Palo Alto CA, US
Assignee:
Winbound Electronics Corporation - Hisn Chu
International Classification:
G06F 13/14
G06F 3/00
G06F 13/42
US Classification:
710305, 710 11, 710105
Abstract:
A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.

Adapter Apparatus For Interfacing An Insertable And Removable Digital Memory Device To A Host Port

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US Patent:
20010038547, Nov 8, 2001
Filed:
Dec 6, 2000
Appl. No.:
09/730925
Inventors:
Robin Jigour - San Jose CA, US
David Wong - San Jose CA, US
International Classification:
G11C005/06
G11C019/08
US Classification:
365/043000, 365/063000, 365/064000, 365/044000
Abstract:
Each device of a family of removable digital media devices may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices and the connector system used by them are compact for minimizing the volume of space occupied in portable devices and for easy storage. Preferably, the digital media devices of the family use serial memory requiring few power and signal lines, so that few electrical contacts are required. For example, a small number of durable contact pads form the contact arrays on the digital media devices, which in conjunction with corresponding contact pads mounted into a suitable socket provide for easy and convenient insertion and removal and for robust and reliable electrical contact over a long insertion lifetime. The digital media devices interface to the host either directly or through adapters.

Serial Flash Semiconductor Memory

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US Patent:
20100049948, Feb 25, 2010
Filed:
Jul 2, 2009
Appl. No.:
12/459590
Inventors:
Robin J. Jigour - San Jose CA, US
Eungjoon Park - Fremont CA, US
Joo Weon Park - Pleasanton CA, US
Jong Seuk Lee - Pal Alto CA, US
Assignee:
Winbond Electronics Corporation - Hisn Chu
International Classification:
G06F 9/30
G06F 12/00
G06F 12/02
US Classification:
712208, 711103, 711E12001, 712E0903
Abstract:
A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.

Flash Memory For Code And Data Storage

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US Patent:
20120084491, Apr 5, 2012
Filed:
Sep 30, 2011
Appl. No.:
13/250077
Inventors:
Eungjoon Park - Fremont CA, US
Robin John Jigour - San Jose CA, US
Jooweon Park - Pleasanton CA, US
Masaru Yano - Tokyo, JP
International Classification:
G06F 12/02
US Classification:
711103, 711E12008
Abstract:
A flash memory for code and data storage includes a code memory array having fast read access and suitability for execute in place, a data memory array having the characteristics of low bit cost and high density storage, and a suitable interface to provide access to both the code and data. The code memory array may be a NOR array or a performance-enhanced NAND array. The memory may be implemented in a single chip package or multi-chip package solution.

Method And Apparatus For Reading Nand Flash Memory

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US Patent:
20130297987, Nov 7, 2013
Filed:
May 4, 2012
Appl. No.:
13/464535
Inventors:
Anil Gupta - Saratoga CA, US
Oron Michael - San Jose CA, US
Robin John Jigour - San Jose CA, US
Assignee:
WINBOND ELECTRONICS CORPORATION - Taichung City
International Classification:
G11C 29/00
G06F 11/16
US Classification:
714773, 714E11054
Abstract:
A page buffer for a NAND memory array has a data register and a cache register that are suitably organized and operated to eliminate gaps and discontinuities in the output data during a continuous page read. The cache register may be organized in two portions, and the page data in the cache may be output from the cache portions in alternation. ECC delay may be eliminated from the output by performing the ECC computation on one cache portion while the other is being output. The data register may also be organized in two portions corresponding to the cache portions, so that data may be transferred to one cache portion while the other is being output. In a variation, the continuous page read may be done without ECC.

On-Chip Bad Block Management For Nand Flash Memory

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US Patent:
20130346671, Dec 26, 2013
Filed:
Jun 22, 2012
Appl. No.:
13/530518
Inventors:
Oron Michael - San Jose CA, US
Robin John Jigour - San Jose CA, US
Anil Gupta - Saratoga CA, US
Assignee:
WINBOND ELECTRONICS CORPORATION - Taichung City
International Classification:
G06F 12/02
US Classification:
711103, 711E12008
Abstract:
Certain functions relating to creation and use of a look-up table for bad block mapping may be implemented “on chip” in the memory device itself, that is on the same die in an additional circuit, or even within the command and control logic of the memory device, so as to reduce the overhead. Moreover, the on-chip implementation of the look-up table may be tightly integrated with other functions of the command and control logic to enable powerful new commands for NAND flash memory, such as a continuous read command and variations thereof.

Insertble And Removable Digital Memory Apparatus

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US Patent:
61755176, Jan 16, 2001
Filed:
Nov 6, 1999
Appl. No.:
9/435495
Inventors:
Robin J. Jigour - San Jose CA
David K. Wong - San Jose CA
Assignee:
Integrated Silicon Solution, Inc. - Santa Clara CA
Nex Flash Technologies, Inc. - Santa Clara CA
International Classification:
G11C 506
US Classification:
365 63
Abstract:
Each device of a family of removable digital media devices (310, 320, 330, 340, 350 and 360) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and the connector system used by the digital media devices are compact for minimizing the volume of space occupied in portable devices and for easy storage. Some embodiments (310, 320, 330, 350 and 360) provide an elongated compact form factor that provides easy and firm grasping for insertion and removal. The digital media devices of the family have respective body portions (312, 322, 332, 342, 352 and 362) preferably of a rigid or semi-rigid material. Preferably, the digital media devices of the family use serial memory requiring few power and signal lines, so that few electrical contacts are required. In particular, a small number of durable contact pads form the contact arrays (314, 324, 334, 344, 354 and 364) on the digital media devices, which in conjunction with corresponding contact pads mounted into a suitable socket provide for easy and convenient insertion and removal and for robust and reliable electrical contact over a long insertion lifetime.

Method And Apparatus For Providing Accessible Device Information In Digital Memory Devices

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US Patent:
59911948, Nov 23, 1999
Filed:
Oct 24, 1997
Appl. No.:
8/957094
Inventors:
Robin J. Jigour - San Jose CA
Asim A. Bajwa - San Jose CA
International Classification:
G11C 1604
G11C 800
US Classification:
36518504
Abstract:
A memory device (100) includes a user device information sector (122) in addition to normal sectors (124) of a memory array. The user device information sector includes a product identification field (240) and a restricted address list field (250), and optionally includes a customer identification number field (220) and a serial number field (230). The product identification field includes such information as the manufacturer ID, a part number ID, package/speed identification, temperature/voltage identification, and byte locations for special options. The device identification field is factory programmed using a high voltage enabling signal applied to a write control logic circuit (102) in the memory device in conjunction with a "Device Information Sector Program" instruction is applied to the SPI command and control logic (110). The device information sector is read from the application using a "Read Device Information" instruction. Inadvertent corruption of the device information sector is avoided since a high voltage typically is not available in the application, and the "Device Information Sector Program" instruction is not in the application command set.
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Robin L Jigour from El Dorado Hills, CA Get Report