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Robert T Trabucco

from Los Altos, CA
Age ~81
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Also known as:
Robert Te Trabucco, Robt T Trabucco, Bob T Trabucco, Rob T Trabucco, Robert T Trabuco, Robert Trabucco C, Robert O
Phone and address:
1300 Ranchita Dr, Los Altos, CA 94024
(650) 823-3806
Related to:
Thomas E Burger, 80Jon Steuer, 70Guillermo Barcenas, 64Tammy K Reynolds, 47Sarah Reynolds
Connected to:
Anthony W Trabucco, 61David M Trabucco, 63Dorcas A Trabucco, 76Jerald A Trabucco, 41Laura M Trabucco, 64Paula J Trabucco, 67Richard J Trabucco, 51Deborah A Trabue, 52Jemay Trabue, 79Kristiana C Trabue, 40

Robert Trabucco Phones & Addresses

  • 1300 Ranchita Dr, Los Altos, CA 94024 (650) 823-3806
  • Los Altos Hills, CA
  • Tahoe Vista, CA
  • San Francisco, CA
  • 5061 Lapa Dr, San Jose, CA 95129
  • Tuscumbia, MO
  • Penn Valley, CA
  • 1300 Ranchita Dr, Los Altos, CA 94024

Business Records

Name / Title
Company / Classification
Phones & Addresses
Robert T. Trabucco
M
Steam Events LLC
1300 Ranchita Dr, Los Altos, CA 94024
1000 Stanley Rd, West Point, CA 95255
4890 Arizona Ave, Las Vegas, NV 89104
1154 Grand Teton Dr, Sharp Park, CA 94044
Robert T. Trabucco
Trabucco Limited Partnership
2172 16 Ave, San Francisco, CA 94116
Robert D Trabucco
Vice President,Treasurer,Director,Trustee
STERLING INC. DBA FRIEDLANDERS JEWELERS

Publications

Us Patents

Method For Planarizing An Array Of Solder Balls

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US Patent:
5901437, May 11, 1999
Filed:
Oct 30, 1997
Appl. No.:
8/960831
Inventors:
Patrick Variot - San Jose CA
Chok J. Chia - Campbell CA
Robert T. Trabucco - Los Altos CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H05K3/34;13/04
US Classification:
29840
Abstract:
A method for mounting an integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit onto to a circuit board. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount. Additionally, the planarized solder ball contacts locally compensate individually for warpage of the integrated circuit package by variation in the individual dimensions of dependency of each solder ball below the bottom surface of the package.

Method Of Planarizing An Array Of Plastically Deformable Contacts On An Integrated Circuit Package To Compensate For Surface Warpage

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US Patent:
57459860, May 5, 1998
Filed:
Jul 24, 1995
Appl. No.:
8/506382
Inventors:
Patrick Variot - San Jose CA
Chok J. Chia - Campbell CA
Robert T. Trabucco - Los Altos CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H05K 334
H05K 1304
US Classification:
29840
Abstract:
A method for mounting an integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit on a circuit board. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount.

Fixture For Attaching Multiple Lids To Multi-Chip Module (Mcm) Integrated Circuit

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US Patent:
54654700, Nov 14, 1995
Filed:
Aug 31, 1994
Appl. No.:
8/299209
Inventors:
Sutee Vongfuangfoo - Sunnyvale CA
Robert Trabucco - Los Altos CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
B25B 2702
US Classification:
29559
Abstract:
A fixture clamps a plurality of lids onto a multi-chip module (MCM) integrated circuit for adhesively attaching the lids to cover a plurality of cavities in the module in which chips or dies are mounted. The fixture includes a base plate which is formed with recesses in which the lids and the module are fittingly retained with the lids properly positioned relative to the module. A pressure plate is guided onto the module by a pin assembly and presses the module against the base plate. A plurality of spring loaded clamps have first jaws that engage with the lids through respective holes in the base plate and second jaws that engage with the pressure plate. The clamp thereby clamps the lids and the pressure plate to the module. The assembly including the module, lids, pressure plate and clamps is then removed from the base plate to enable curing of an adhesive that bonds the lids to the module, and frees the base plate for reuse.

Integrated Circuit Having A Coplanar Solder Ball Contact Array

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US Patent:
54354820, Jul 25, 1995
Filed:
Feb 4, 1994
Appl. No.:
8/192081
Inventors:
Patrick Variot - San Jose CA
Chok J. Chia - Campbell CA
Robert T. Trabucco - Los Altos CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 21603
US Classification:
228254
Abstract:
An integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount. Additionally, the planarized solder ball contacts locally compensate individually for warpage of the integrated circuit package by variation in the individual dimensions of dependency of each solder ball below the bottom surface of the package.

Casting Of Raised Bump Contacts On A Substrate

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US Patent:
53818482, Jan 17, 1995
Filed:
Sep 15, 1993
Appl. No.:
8/121676
Inventors:
Robert T. Trabucco - Los Altos CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
B23K 300
US Classification:
164102
Abstract:
A technique for simultaneously forming large numbers of solder ball (or bump) contacts on a surface of a substrate is described. A mold is provided for receiving a substrate. Recesses in the mold are shaped to form contacts of a desired size, and are arranged to align with contact pads on the surface of the substrate. When the substrate is inserted into the mold and the mold is closed, the contact pads align with the recesses. Molten solder is introduced into the recesses and, upon cooling, forms conductive raised bump contacts on the contact pads. The substrate is then removed from the mold. Various features of the invention are directed to forming "tall" contacts with an aspect ratio (height to width ratio) of greater than 1:1, processing more than one substrate at a time, processing substrates of different sizes, and processing substrates with different contact patterns.

Conductive Polymer Ball Attachment For Grid Array Semiconductor Packages

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US Patent:
57610487, Jun 2, 1998
Filed:
Apr 16, 1996
Appl. No.:
8/632952
Inventors:
Robert T. Trabucco - Los Altos CA
Assignee:
LSI Logic Corp. - Milpitas CA
International Classification:
H05K 114
US Classification:
361760
Abstract:
According to the present invention, a method is provided for attaching a package substrate to a circuit board. In one version of the invention, the package substrate has a semiconductor die disposed thereon, and the semiconductor die has a plurality of bond pads formed thereon which are electrically connected to conductive traces on the package substrate. In one embodiment of the invention, the method comprises the steps of attaching a first surface of an electrical connector to one of the conductive traces by thermoplastic adhesion; and attaching a second surface of the electrical connector to a conducting pad on the circuit board, also by thermoplastic adhesion.

Semiconductor Device Package Fabrication Method And Apparatus

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US Patent:
56104421, Mar 11, 1997
Filed:
Mar 27, 1995
Appl. No.:
8/412087
Inventors:
Mark R. Schneider - San Jose CA
Robert T. Trabucco - Los Altos CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 2328
H01L 2310
H01L 2348
US Classification:
257787
Abstract:
A planar substrate is attached to a face of a semiconductor die. The semiconductor die is electrically connected to a printed wiring board and encapsulation material covers the peripheral edges of the planar substrate, semiconductor die, and means for interconnecting the die and printed wiring board. An exterior face of the planar substrate remains exposed and may be utilized in pick and place automatic assembly. The exterior face of the planar substrate may also be utilized for attachment of an external heat sink for improved heat transfer from the semiconductor device. The planar substrate may be comprised of silicon, ceramic, metal or any other stiff material so long as the temperature coefficient of expansion is similar to that of the semiconductor die. A flip-chip semiconductor die may also be utilized without a planar substrate wherein the nonactive face of the die is exposed.

Fabrication Of A Dissolvable Film Carrier Containing Conductive Bump Contacts For Placement On A Semiconductor Device Package

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US Patent:
53883276, Feb 14, 1995
Filed:
Sep 15, 1993
Appl. No.:
8/122027
Inventors:
Robert T. Trabucco - Los Altos CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H05K 334
US Classification:
29830
Abstract:
A technique for simultaneously forming large numbers of solder ball (or bump) contacts on a surface of a substrate is described. A dissolvable film carrier is provided with holes arranged in a shape to correspond to an array of contact pads on a substrate. The holes are filled with solder. The film carrier retains the solder. The carrier is placed over the surface of the substrate and is heated, causing the solder to re-flow and to wet and to adhere to the contact pads. The carrier, which resists the re-flow temperature, maintains the shape of the solder contacts while cooling. After cooling, the film carrier can be removed from around the solder contacts with a suitable solvent.
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Robert T Trabucco from Los Altos, CA, age ~81 Get Report