Robert S Fairfield

54427690, Aug 15, 1995

Apr 7, 1993

8/044556

Gary T. Corcoran - Fanwood NJ
Robert C. Fairfield - Randolph NJ

AT&T Corp. - Murray Hill NJ

G06F 1204
G06F 934

395310

A processor specially adapted for use as a coprocessor. The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which receives an input which determines whether the microprocessor operates as a bus master or a bus slave. Certain output pins have three-state bus drivers which employ feedback to ensure that a signal on a line being driven by the driver has gone inactive before the driver is turned off. Instructions executed by the microprocessor permit specification of portions of the internal registers as sources and destinations and specification of the size of an ALU operation, permitting easy operation on data ranging from bytes through 24-bit pointers. Instructions are executed in an instruction pipeline and a separate I/O instruction pipeline. Some pipeline stalls are avoided by means of a special MOVE instruction which differs from an ordinary MOVE instruction in that it does not cause pipeline stall when it reads data from a register loaded by a preceding READ instruction.

54468655, Aug 29, 1995

Mar 13, 1990

7/493018

Gary T. Corcoran - Fanwood NJ
Robert C. Fairfield - Randolph NJ
Akkas T. Sufi - Somerset NJ

AT&T Corp. - Murray Hill NJ

G06F 300
G06F 500

395500

A processor specially adapted for use as a coprocessor. The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which receives an input which determines whether the microprocessor operates as a bus master or a bus slave. Certain output pins have three-state bus drivers which employ feedback to ensure that a signal on a line being even by the driver has gone inactive before the driver is turned off. Instructions executed by the microprocessor permit specification of portions of the internal registers as sources and destinations and specification of the size of an ALU operation, permitting easy operation on data ranging from bytes through 24-bit pointers. Instructions are executed in an instruction pipeline and a separate I/O instruction pipeline. Some pipeline stalls are avoided by means of a special MOVE instruction which differs from an ordinary MOVE instruction in that it does not cause pipeline stall when it reads data from a register loaded by a preceding READ instruction.

55131816, Apr 30, 1996

Feb 17, 1995

8/390333

Robert D. Bresalier - Parsippany NJ
Robert C. Fairfield - Randolph NJ
Kevin Loughran - Randolph Township, Morris County NJ

AT&T Corp. - Murray Hill NJ

H04J 302

370 79

A multi-signal multi-coder transcoder is disclosed for communications systems that can be fabricated less expensively than embodiments in the prior art and without requiring significant changes to the signal source and destination devices. An illustrative embodiment preferably comprises an input lead, an output lead, an input switch, an output switch, a pool of N processing elements, which are configured to perform a first coding technique and a pool of M processing elements, which are configured to perform a second coding technique, or possibly both techniques. When the input lead carries a plurality of multiplexed signals, each of which is to be transcoded in accordance with one of the two coding techniques, the input switch segregates and routes the incoming signals to an appropriate processing element. While a processing element is preferably configured to perform only one coding technique, each is preferably capable of transcoding multiple signals concurrently in accordance with that technique. The output switch gathers the respective transcoded signals, re-multiplexes them and transmits them on the output lead.

53275373, Jul 5, 1994

May 18, 1993

8/063354

Gary T. Corcoran - Fanwood NJ
Robert C. Fairfield - Randolph NJ

AT&T Bell Laboratories - Murray Hill NJ

G06F 938

395375

A processor which is specially adapted for use as a coprocessor. The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which receives an input which determines whether the microprocessor operates as a bus master or a bus slave. Certain output pins have three-state bus drivers which employ feedback to ensure that a signal on a line being driven by the driver has gone inactive before the driver is turned off. Instructions executed by the microprocessor permit specification of portions of the internal registers as sources and destinations and specification of the size of an ALU operation, permitting easy operation on data ranging from bytes through 24-bit pointers. Instructions are executed in an instruction pipeline and a separate I/O instruction pipeline. Some pipeline stalls are avoided by way of a special MOVE instruction which differs from an ordinary MOVE instruction in that it does not cause pipeline stall when it reads data from a register loaded by a preceding READ instruction.

52789594, Jan 11, 1994

Mar 13, 1993

7/490172

Gary T. Corcoran - Fanwood NJ
Robert C. Fairfield - Randolph NJ

AT&T Bell Laboratories - Murray Hill NJ

G06F 1336

395325

A processor specially adapted for use as a coprocessor The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which receives an input which determines whether the microprocessor operates as a bus master or a bus slave. Certain outputs pins have three-state bus drivers which employ feedback to ensure that a signal on a line being driven by the driver has gone inactive before the driver is turned off. Instructions executed by the microprocessor permit specification of portions of the internal registers as sources and destinations and specification of the size of an ALU operation, permitting easy operation on data ranging from bytes through 24-bit pointers. Instructions are executed in an instruction pipeline and a separate I/O instruction pipeline. Some pipeline stalls are avoided by means of a special MOVE instruction which differs from an ordinary MOVE instruction in that it does not cause pipeline stall when it reads data from a register loaded by a preceding READ instruction.

50291637, Jul 2, 1991

Mar 18, 1988

7/169687

Phillip C. J. Chao - Naperville IL
Bong S. Choe - Lebanon NJ
Robert C. Fairfield - Randolph NJ
Thomas L. Hiller - Glen Ellyn IL
Robert W. King - Naperville IL
Joel D. Peshkin - Heidelberg Township, Lehigh County PA
Ralph A. Wilson - Wheaton IL

AT&T Bell Laboratories - Murray Hill NJ

H04J 316

370 951

A synchronous protocol data formatter handles all 24-32 channels of a so-called primary rate version of a digital multiplexed interface or ISDN Primary Rates Interface for a communication system. The formatter relieves the host computer of the local area network of some highly specialized tasks, and, at the same time, provides the following augmented capabilities, which exceed those required by the C. C. I. T. T. standard, I. 431: 1. dynamic channel bandwidth allocation can assign arbitrary (even non-adjacent) time slots to create a super channel; 2. a circular interrupt-queue in a shared memory enables the formatter and the host computer of the local area network to interact efficiently in updating and responding to changing conditions; and 3. cyclical redundancy codes can be used on a more flexible basis than theretofore, e. g. , can be generated upon only address and control fields for digitized voice signals, or, in a relay mode, can substitute an existing cyclical redundancy code to guard against memory errors.