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Robert Arthur Ertl

from Santa Cruz, CA
Age ~66
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Also known as:
Robert A Ertl, Robert R Ertl, Roberta Ertl, Bob A Ertl, Rob A Ertl, Robert Smith, Dayanna Macias
Phone and address:
138 Seaside St, Santa Cruz, CA 95060
(831) 423-8241
Related to:
Deborah L Smith, 67Lindsay K Alexander, 38Haley A Ertl, 85Preston R Smith, 51Michelle A Smith, 66Debbie F Smith, 91Adam S Alexander, 40Gerry D Phipps, 71Margarita C Smith, 60
Connected to:
Allison C Ertl, 45David J Ertl, 57Debora A Ertl, 62Delia Ertl, 83Elizabeth K Ertl, 35Gretchen A Ertl, 52Jeff P Ertl, 59Jonathan W Ertl, 41Lara Ertl, 49Lynn G Ertl, 68

Robert Ertl Phones & Addresses

  • 138 Seaside St, Santa Cruz, CA 95060 (831) 423-8241 (831) 713-5555
  • Bloomfield Hills, MI
  • 204 Lester Ln, Los Gatos, CA 95032
  • 1641 Glenroy Dr, San Jose, CA 95124
  • Manchaca, TX
  • Los Angeles, CA
  • Lewisville, TX
  • Salinas, CA
  • Oakland, MI
  • Travis, TX

Publications

Us Patents

Chameleon Measure And Metric Calculation

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US Patent:
6732115, May 4, 2004
Filed:
Apr 27, 2001
Appl. No.:
09/844488
Inventors:
Arun Shah - Saratoga CA
Robert F. Novy - Redwood City CA
Robert A. Ertl - Los Gatos CA
Assignee:
Hyperion Solutions Corporation - Sunnyvale CA
International Classification:
G06F 1730
US Classification:
707102
Abstract:
Disclosed is a system, method, and apparatus for calculating metrics by using hierarchical level metadata to describe the various structures within the database. The hierarchical level metadata permit calculation of complex metrics by an analytical server which would otherwise be difficult or impossible. As a result of the way that the analytical server calculates the metrics, slicing and drilling are supported. Additionally, dimension and fact level security are also supported.

Graphical User Interface For Relational Database

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US Patent:
6748394, Jun 8, 2004
Filed:
Apr 27, 2001
Appl. No.:
09/844680
Inventors:
Arun Shah - Saratoga CA
Robert F. Novy - Redwood City CA
Robert A. Ertl - Los Gatos CA
Assignee:
Hyperion Solutions Corporation - Sunnyvale CA
International Classification:
G06F 1730
US Classification:
707102, 7071041
Abstract:
Disclosed is a system, method, and apparatus for calculating metrics by using hierarchical level metadata to describe the various structures within the database. The hierarchical level metadata permit calculation of complex metrics by an analytical server which would otherwise be difficult or impossible. As a result of the way that the analytical server calculates the metrics, slicing and drilling are supported. Additionally, dimension and fact level security are also supported.

Aggregate Navigation System

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US Patent:
6941311, Sep 6, 2005
Filed:
Apr 27, 2001
Appl. No.:
09/844700
Inventors:
Arun Shah - Saratoga CA, US
Robert F. Novy - Redwood City CA, US
Robert A. Ertl - Los Gatos CA, US
Assignee:
Hyperion Solutions Corporation - Sunnyvale CA
International Classification:
G06F017/00
US Classification:
707101, 707 3, 707102
Abstract:
Disclosed is a system, method, and apparatus for calculating metrics by using hierarchical level metadata to describe the various structures within the database. The hierarchical level metadata permit calculation of complex metrics by an analytical server which would otherwise be difficult or impossible. As a result of the way that the analytical server calculates the metrics, slicing and drilling are supported. Additionally, dimension and fact level security are also supported.

Non-Additive Measures And Metric Calculation

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US Patent:
7072897, Jul 4, 2006
Filed:
Apr 27, 2001
Appl. No.:
09/844483
Inventors:
Arun Shah - Saratoga CA, US
Robert F. Novy - Redwood City CA, US
Robert A. Ertl - Los Gatos CA, US
Assignee:
Hyperion Solutions Corporation - Sunnyvale CA
International Classification:
G06F 17/00
US Classification:
707101
Abstract:
Disclosed is a system, method, and apparatus for calculating metrics by using hierarchical level metadata to describe the various structures within the database. The hierarchical level metadata permit calculation of complex metrics by an analytical server which would otherwise be difficult or impossible. As a result of the way that the analytical server calculates the metrics, slicing and drilling are supported. Additionally, dimension and fact level security are also supported.

Allocation Measures And Metric Calculations In Star Schema Multi-Dimensional Data Warehouse

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US Patent:
7080090, Jul 18, 2006
Filed:
Apr 27, 2001
Appl. No.:
09/844706
Inventors:
Arun Shah - Saratoga CA, US
Robert F. Novy - Redwood City CA, US
Robert A. Ertl - Los Gatos CA, US
Assignee:
Hyperion Solutions Corporation - Sunnyvale CA
International Classification:
G06F 17/30
US Classification:
707102, 707101, 707100
Abstract:
Disclosed is a system, method, and apparatus for calculating metrics by using hierarchical level metadata to describe the various structures within the database. The hierarchical level metadata permit calculation of complex metrics by an analytical server which would otherwise be difficult or impossible. As a result of the way that the analytical server calculates the metrics, slicing and drilling are supported. Additionally, dimension and fact level security are also supported.

Database Security

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US Patent:
7167859, Jan 23, 2007
Filed:
Apr 27, 2001
Appl. No.:
09/844717
Inventors:
Arun Shah - Saratoga CA, US
Robert F. Novy - Redwood City CA, US
Robert A. Ertl - Los Gatos CA, US
Assignee:
Hyperion Solutions Corporation - Santa Clara CA
International Classification:
G06F 7/00
G06F 17/30
US Classification:
707 9, 707 2, 707 7, 707 10, 726 27
Abstract:
Disclosed is a system, method, and apparatus for calculating metrics by using hierarchical level metadata to describe the various structures within the database. The hierarchical level metadata permit calculation of complex metrics by an analytical server which would otherwise be difficult or impossible. As a result of the way that the analytical server calculates the metrics, slicing and drilling are supported. Additionally, dimension and fact level security are also supported.

Computer System Architecture Employing Cache Data Line Move-Out Queue Buffer

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US Patent:
48811637, Nov 14, 1989
Filed:
Sep 19, 1986
Appl. No.:
6/909500
Inventors:
Jeffrey A. Thomas - Cupertino CA
Theodore S. Robinson - Cupertino CA
Robert A. Ertl - Santa Clara CA
Harold F. Christensen - Fremont CA
Assignee:
Amdahl Corporation - Sunnyvale CA
International Classification:
G06F 1300
US Classification:
364200
Abstract:
A queue buffer used for the controlled buffering and transferal of data between a cache memory of a central processor unit and a mainstore memory unit. The queue buffer of the present invention preferably includes a buffer memory for the queued storage of data and a controller for directing the nominally immediate acceptance and storage of data received direct from a cache memory and for the nominally systematic background transfer of data from the queue buffer to the mainstore memory unit. This nominal prioritization of memory transfers with respect to the queue buffer memory allows data move-in requests requiring data from the main storage unit to proceed while required move-out data is moved from a cache memory immediately to the buffer queue memory.

Computer System Architecture Implementing Split Instruction And Operand Cache Line-Pair-State Management

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US Patent:
50954245, Mar 10, 1992
Filed:
Jul 21, 1989
Appl. No.:
7/384867
Inventors:
Gary A. Woffinden - Scotts Valley CA
Theodore S. Robinson - Cupertino CA
Jeffrey A. Thomas - Cupertino CA
Robert A. Ertl - Santa Clara CA
James P. Millar - Santa Clara CA
Christopher D. Finan - Santa Clara CA
Joseph A. Petolino - Palo Alto CA
Ajay Shah - San Jose CA
Shen H. Wang - San Jose CA
Mark Semmelmeyer - Sunnyvale CA
Assignee:
Amdahl Corporation - Sunnyvale CA
International Classification:
G06F 1202
US Classification:
395425
Abstract:
A computer system architecture implementing multiple central processing units, each including a split instruction and operand cache, and that provides for the management of multiple copies (line pairs) of a memory line through the use of a line pair state is described. Systematic management of memory lines when transferred with respect to instruction and operand data cache memories allows the integrity of the system to be maintained at all times. The split cache architecture management determines whether a memory line having a first predetermined system address is present within both the instruction and operand cache memories or will be upon move-in of a memory line. Address tag line pair state information is maintained to allow determinations of whether and where the respective memory line pair members reside. The architecture implements the management of the line pairs on each transfer of a memory line to any of the split caches of the system. A line pair is allowed to exist whenever the same memory line exists in the same relative location in each of the instruction and operand cache buffers of a single central processor.
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Robert Arthur Ertl from Santa Cruz, CA, age ~66 Get Report