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Robert C Chiraz

from Nesconset, NY
Age ~67

Robert Chiraz Phones & Addresses

  • 9 Wiigs Rd, Nesconset, NY 11767 (631) 361-9172
  • Hauppauge, NY
  • 4843 206Th St, Oakland Gardens, NY 11364 (718) 423-8368
  • Oakland Gdns, NY

Work

Company: Small computing research company Sep 2018 Position: Senior principal engineer

Education

Degree: Master of Science, Masters Specialities: Electrical Engineering

Skills

Systems Engineering • Electronics • Digital Circuit Design • Analog Circuit Design • Orcad Schematic Capture • Pcb Design • Cadence Allegro • Smart Antennas • Mimo • Digital Signal Processing • Simulations • Pspice • Microsoft Excel • C Language • Testing • Assembly Language • Mosfet • Power Electronics Design

Languages

English

Industries

Computer & Network Security

Resumes

Resumes

Robert Chiraz Photo 1

Senior Principal Engineer

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Location:
9 Wiigs Rd, Nesconset, NY 11767
Industry:
Computer & Network Security
Work:
Small Computing Research Company
Senior Principal Engineer

Computing Research Company
Senior Electronic Designer

L-3 Communications Sep 2003 - Mar 2017
Principal Engineer - Narda Miteq, An L3 Company
Skills:
Systems Engineering
Electronics
Digital Circuit Design
Analog Circuit Design
Orcad Schematic Capture
Pcb Design
Cadence Allegro
Smart Antennas
Mimo
Digital Signal Processing
Simulations
Pspice
Microsoft Excel
C Language
Testing
Assembly Language
Mosfet
Power Electronics Design
Languages:
English

Business Records

Name / Title
Company / Classification
Phones & Addresses
Robert Chiraz
CONCISE MULTIMEDIA & COMMUNICATIONS INC
9 Wiigs Rd, Nesconset, NY 11767

Publications

Us Patents

Method And Apparatus For Addressing Multiple Frame Buffers

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US Patent:
6411302, Jun 25, 2002
Filed:
Jan 6, 1999
Appl. No.:
09/226350
Inventors:
Robert Carmine Chiraz - Nesconset NY
Assignee:
Concise Multimedia and Communications Inc. - Nesconset NY
International Classification:
G09G 536
US Classification:
345545, 345543, 345544, 345531, 345537, 348552
Abstract:
High resolution image data is stored in multiple frame buffers to enable the image data to be coupled to multiple lower resolution video streams. Despite physical address discontinuities at frame buffer crossover boundaries, addressing of the multiple frame buffers as a single logical frame buffer is made possible by first dividing the image data into pages using a page size appropriate for both the video mode and arrangement of the physical frame buffers within the high resolution image. Then a pitch is determined for each of the physical frame buffers that enables the alignment of the memory pages at the frame buffer crossovers. Then for video modes utilizing multiple bytes per pixel, the collection of bytes representing the pixels are aligned on the page boundaries at the frame buffer crossovers. Then linear address space is reserved for storing a single high resolution frame buffer. Then address translation hardware is configured to shuffle the mapping of the pages such that the pages within the reserved linear address space are routed to the appropriate pages within the multiple physical frame buffers to create a single high resolution frame buffer when accessed with an appropriate logical pitch.
Robert C Chiraz from Nesconset, NY, age ~67 Get Report