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Richard D Duce

from San Jose, CA
Age ~62
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Also known as:
Richard David John Duce, Richard David Duce, Richard John Duce, Richard L Duce, Richard J Duce, Duce Richard John, H Duce, John Richard Duce, Richard David N
Phone and address:
3112 Mattique Dr, San Jose, CA 95135
(408) 531-1585
Related to:
Jung S Lee, 76
Connected to:
Amy Duce, 44Brittany L Duce, 34David R Duce, 53Elizabeth M Duce, 77Henrietta J Duce, 80Holly R Duce, 46Jenny B Duce, 74Jonathan R Duce, 40Laura L Duce, 58Richard Duce, 56

Richard Duce Phones & Addresses

  • 3112 Mattique Dr, San Jose, CA 95135 (408) 531-1585
  • The Villages, FL
  • Fremont, CA
  • Mariposa, CA
  • Austin, TX
  • Santa Clara, CA
  • Riverside, CA
  • 3112 Mattique Dr, San Jose, CA 95135

Work

Position: Farming-Forestry Occupation

Education

Degree: High school graduate or higher

Resumes

Resumes

Richard Duce Photo 1

Richard Duce

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Xilinx
Product Manager
Skills:
Eda
Verilog
Ic
Asic
Product Management
Tcl
Semiconductors
Fpga
Rtl Design
Soc
Functional Verification
Static Timing Analysis
Electronics
Simulations
Field Programmable Gate Arrays
Integrated Circuits
Richard Duce Photo 2

Richard Duce

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Richard Duce Photo 3

Senior Systems Analyst At Quadramed

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Position:
Query Writer at High Desert Health Systems, Senior Systems Analyst at Quadramed Corporation
Location:
West Hills, California
Industry:
Computer Software
Work:
High Desert Health Systems - Lancaster, CA since Nov 2011
Query Writer
Quadramed Corporation since Apr 2007
Senior Systems Analyst
Olive View - UCLA Medical Center - Sylmar, CA Apr 2007 - Oct 2011
Query Writer
CountryWide Warehouse Lending Division May 2006 - Sep 2006
Financial Analyst
PeopleQuest Aug 2005 - May 2006
Client Services
Education:
University of Phoenix 2004 - 2005
California State University 2000
B.S. Health Science, Option; Health Administration
Skills:
J-Reports
Crystal Reports
Affinity

Publications

Us Patents

Circuits And Methods For Characterizing The Speed Performance Of Multi-Input Combinatorial Logic

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US Patent:
6850123, Feb 1, 2005
Filed:
May 27, 2003
Appl. No.:
10/447132
Inventors:
Himanshu J. Verma - Mountain View CA, US
Anthony P. Calderone - Soquel CA, US
Richard D. Duce - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03B 2700
US Classification:
331 57, 331DIG 3
Abstract:
A test oscillator circuit separately measures the signal propagation delay for both rising and falling edges through one or more multi-input combinatorial logic circuits. A number of components are configured in a loop so that they together form a free-running ring oscillator. Each synchronous component passes signal edges to a subsequent component in the ring, so the oscillator produces an oscillating test signal in which the period relates to the delays through the components. In some embodiments, the multi-input combinatorial logic circuits emulate tri-state buffers. These embodiments characterize the speed at which these logic circuits enable and disable signal paths.
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Richard D Duce from San Jose, CA, age ~62 Get Report