Richard D Allison

44384483, Mar 20, 1984

Jul 18, 1980

6/170131

Alan L. Harrington - Glendale CA
Richard Allison - Los Angeles CA
Vladimir Rodov - North Hollywood CA

TRW Inc. - Los Angeles CA

H01L 21302
H01L 2904
H01L 2978

357 23

A zig-zag V-groove configuration for use in V-MOS transistors is disclosed. Instead of merely forming parallel rows of V-grooves, a zig-zag configuration is used, utilizing two different directions for the V-grooves, at least one of which is not the conventional direction. This configuration can be used with either the ladder or interdigitated configuration for the source contact and gate metals.

43286119, May 11, 1982

Apr 28, 1980

6/144672

Alan L. Harrington - Glendale CA
Richard Allison - Los Angeles CA

TRW Inc. - Los Angeles CA

H01L 2120
H01L 2174

29580

A bipolar semiconductor is manufactured by forming a plurality of grooves along the vertical (111) planes in a high resistivity epitaxial silicon layer which is disposed on an N+ (110) oriented substrate. Low resistivity epitaxial silicon of the same conductivity type is then used to fill in the grooves, thus forming alternate vertical regions of high and low resistivity. A base region is then diffused into said epitaxial layer and a plurality of emitters regions are diffused into said base region at locations directly above the low resistivity epitaxial regions.

42952670, Oct 20, 1981

Jul 18, 1980

6/170144

Alan L. Harrington - Glendale CA
Vladimir Rodov - Hollywood CA
Richard Allison - Los Angeles CA

TRW Inc. - Los Angeles CA

H01L 2120

29571

A simplified method of fabricating V-groove junction field effect transistors using only two masking steps. The first masking step opens regions in an ohmic refractory metal layer deposited on a doped semiconductor wafer. V-grooves are anisotropically etched into the wafer through the openings, thereby defining source and drain regions and outer isolation V-grooves. The wafer is then coated with a passivating layer. The second masking step creates openings through the passivation layer to the source and drain regions, and electrical contacts to those regions are made. An ohmic contact to the back surface of the wafer forms the gate electrode. Multiple source and drain regions may be created between the outer isolation V-grooves and electrically parallel for a greater current rating.