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Rex T Baird

from Bozeman, MT
Age ~60
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Also known as:
Rex Thomas Baird, Rex T Barid
Phone and address:
8511 W Panorama Dr, Bozeman, MT 59715
(406) 587-2038
Related to:
Steven H Stark, 52Caitlin C BairdNicole Beal, 46Catherine Baird, 26Joel Stark, 43
Connected to:
Al E Baird, 67Alberta L Baird, 67Alexa G Baird, 35Allison Baird, 44Alonda L Baird, 41Angelika Baird, 75Anna M Baird, 61Aundrea E Baird, 58Blaine R Baird, 39Britt M Baird, 50

Rex Baird Phones & Addresses

  • 8511 W Panorama Dr, Bozeman, MT 59715 (406) 587-2038
  • Eagle Pass, TX
  • 40 Barrington Ave, Nashua, NH 03062
  • 4832 Calhoun Canyon Loop, Austin, TX 78735
  • Pullman, WA
  • Vancouver, WA

Resumes

Resumes

Rex Baird Photo 1

Owner

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Location:
Bozeman, MT
Industry:
Electrical/Electronic Manufacturing
Work:
Nu Trek Feb 2009 - Jan 2011
Director of Engineering
Nu-Trek Sep 2008 - Jan 2009
Senior Design Engineer
Cascade Technology Feb 2006 - May 2008
Engineering Consultant
Montana State University Jun 2005 - May 2007
Adjunct Professor
Cascade Technology Jun 2005 - May 2007
Owner
Education:
Washington State University 1991 - 1994
Master of Science, Doctorates, Masters, Doctor of Philosophy, Electrical Engineering, Philosophy Montana State University - Bozeman 1982 - 1986
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Start Ups
Semiconductors
Product Development
Embedded Systems
Electronics
Electricians
Pcb Design
Software Development
Project Management
Testing
Telecommunications
Manufacturing
Electrical Engineering
Product Management
Engineering
C
Rex Baird Photo 2

Rex Baird

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Rex Baird Photo 3

Rex Baird

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Rex T. Baird
Owner
Riela Homes, LLC
Business Services at Non-Commercial Site · Nonclassifiable Establishments
8511 W Panorama Dr, Bozeman, MT 59715
Rex T. Baird
Principal
Cascade Technology, LLC
Business Services
8511 W Panorama Dr, Bozeman, MT 59715
Rex Baird
Rexercise
Fitness Consultants
283 Mt Auburn St #A, Watertown, MA 02472
(617) 923-0010

Publications

Us Patents

Optical Disk Pickup System Using Current Division Signal Transmission And Methods And Optical Disk Systems Using The Same

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US Patent:
6418110, Jul 9, 2002
Filed:
Oct 31, 2000
Appl. No.:
09/703315
Inventors:
Rex Baird - Austin TX
Assignee:
Cirrus Logic Inc.
International Classification:
G11B 700
US Classification:
3691241, 36912412, 369 4441
Abstract:
An optical disk pickup system using current mode signal transmission is disclosed. An operational amplifier has an input for receiving an electrical signal and a feedback loop including a current path of a first transistor of a first size, transistor having a control terminal at a preselected voltage. A conductor is coupled to an output of operational amplifier for transmitting the electrical signal as a current. A second transistor of a second size has a current path in series with a conductor and a control terminal coupled to the preselected voltage, transistors forming a current divider.

Multi-Bank Flash Adc Array With Uninterrupted Operation During Offset Calibration And Auto-Zero

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US Patent:
6459394, Oct 1, 2002
Filed:
May 22, 2001
Appl. No.:
09/863205
Inventors:
Itani R. Nadi - Austin TX
Rex Baird - Austin TX
Matthew M. Kostelnik - Arvada CO
Mokry Wesley - Austin TX
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
H03M 110
US Classification:
341120, 341155
Abstract:
A system and method is disclosed for calibrating comparators of an ADC while the ADC continues to operate in an uninterrupted fashion. Groups (banks) of interleaved comparators may be calibrated at random or psuedo-random times while the ADC is performing conversions without the addition of extra âproxyâ or replacement comparators. More particularly, at periodic intervals the comparators of one bank may be disconnected from the standard ADC circuitry for calibration or auto-zeroing while the comparators in the remaining bank(s) are left in the data conversion path. In order to prevent a significant degradation in the conversion quality, logic downstream of the comparators provides the necessary adjustments to accommodate for the removal of the comparators and outputs a word of the desired bit length. The multi-bank ADC is particularly advantageous for use with optical data storage systems.

Optical Servo Control Circuits And Methods Using Pulse Width Modulation And Offset Control For Driving An Electromechanical Motor

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US Patent:
6552979, Apr 22, 2003
Filed:
Oct 30, 2000
Appl. No.:
09/702174
Inventors:
Wesley Ladd Mokry - Austin TX
Rex Thomas Baird - Austin TX
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
G11B 1552
US Classification:
369 4738, 369 4748, 369 4749, 369 4411, 369 533
Abstract:
Servo control circuitry includes a digital to analog converter for converting digital servo control data into a pulse width modulated signal. A first conductor transmits the pulse width modulated signal to an external device. A second conductor transmits a reference signal derived from the clock signal to external device , external device differentially receiving the pulse width modulated signal with respect to the reference signal.

Digitally-Synthesized Loop Filter Circuit Particularly Useful For A Phase Locked Loop

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US Patent:
6630868, Oct 7, 2003
Filed:
Jul 10, 2001
Appl. No.:
09/902541
Inventors:
Michael H. Perrott - Cambridge MA
Rex T. Baird - Austin TX
Yunteng Huang - Austin TX
Assignee:
Silicon Laboratories, Inc. - Austin TX
International Classification:
H03B 524
US Classification:
331 17, 331 1 A, 331177 R, 331158, 375376, 375373
Abstract:
In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In a preferred embodiment, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i. e. , discrete-time and discrete-value) signal. This digital phase error signal is âintegratedâ by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator. The equivalent âsizeâ of the integrating capacitor function provided by the digital integration block may be varied by increasing or decreasing the bit resolution of circuits within the digital block. Consequently, an increasingly larger equivalent capacitor may be implemented by adding additional digital stages, each of which requires a small incremental integrated circuit area.

Optical Disk Pickup Using Current Mode Signal Exchanges And Systems And Methods Using The Same

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US Patent:
6650614, Nov 18, 2003
Filed:
Oct 30, 2000
Appl. No.:
09/702240
Inventors:
David Michael Pietruszynski - Austin TX
Rex Baird - Austin TX
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
G11B 700
US Classification:
3691241, 369120, 36911227
Abstract:
An optical disk pickup system includes an array of photodiodes for converting photons reflected from an optical disk into a plurality of electrical signals each representing a channel. Driving circuitry drives at least one of the electrical signals as a current across a conductor of a flexible cable. A low impedance load converts the electrical signal driven across the conductor as a current into a voltage for further processing.

Integrated Circuit Incorporating Circuitry For Determining Which Of At Least Two Possible Frequencies Is Present On An Externally Provided Reference Signal And Method Therefor

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US Patent:
6686803, Feb 3, 2004
Filed:
Jul 10, 2001
Appl. No.:
09/902543
Inventors:
Michael H. Perrott - Cambridge MA
Jerrell P. Hein - Driftwood TX
Rex T. Baird - Austin TX
Assignee:
Silicon Laboratories, Inc. - Austin TX
International Classification:
H03L 7089
US Classification:
331 10, 331107, 331173, 331117 R
Abstract:
An internal frequency reference, such as a VCO used in a PLL, having a free-running frequency fairly well controlled within a predictable range, is used as a rough frequency reference to determine, for an externally-provided frequency reference signal, which of a finite number of discrete frequencies is currently received. The VCO has a frequency range which varies less, as a percentage, than the ratio between possible reference frequency values. Consequently, the VCO is used as a frequency reference to measure the frequency reference signal. An internal signal is generated to indicate to remaining circuitry which of the possible reference frequencies is actually being provided, without requiring use of any dedicated input pins to receive a select signal. An integrated circuit device may be configured for different modes of operation as a function of which reference frequency is provided to the device. Moreover, if one of the available reference clock frequencies is chosen to correspond to an internal test mode, the device may be placed in a test mode without requiring any additional dedicated input pins for that purpose, either.

Impedance Tuning Circuit

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US Patent:
6753738, Jun 22, 2004
Filed:
Jun 25, 2002
Appl. No.:
10/180783
Inventors:
Rex T. Baird - Nashua NH
Assignee:
Silicon Laboratories, Inc. - Austin TX
International Classification:
H03L 700
US Classification:
331 25, 331167, 331177 R, 331117 FE, 331177 Y
Abstract:
A feedback system such as a phase locked loop (PLL) includes a second feedback loop which responds when a VCO control voltage is near either end of its range, by slowly adjusting additional tuning elements which control the VCO frequency. The second feedback loop is arranged to cause a slow enough change in the VCO frequency that the first traditional feedback loop adjusts the control voltage quickly enough in a direction toward its mid-range value to keep the VCO frequency substantially unchanged. The second feedback loop advantageously incorporates one or more digital control signals which preferably change no more than one bit at a time and with a controlled slow ramp rate. As a result, the PLL maintains phase accuracy so that the operation of the PLL, including subtle specifications such as input data jitter tolerance or output jitter generation when used for clock and data recovery applications, is not negatively impacted. An impedance tuning feedback system provides a resistance between two nodes which is proportional to a reference resistance, and preferably incorporates slow digital switching to result in near perturbation-free state changes over the tuning range of the resistance.

Optical Disk Pickup Using Current Mode Signal Exchanges And Systems And Methods Using The Same

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US Patent:
7031236, Apr 18, 2006
Filed:
Sep 18, 2003
Appl. No.:
10/664688
Inventors:
David Michael Pietruszynski - Austin TX, US
Rex Baird - Austin TX, US
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
G11B 7/00
US Classification:
369 4441, 36912412
Abstract:
An optical disk pickup system includes an array of photodiodes for converting photons reflected from an optical disk into a plurality of electrical signals each representing a channel. Driving circuitry drives at least one of the electrical signals as a current across a conductor of a flexible cable A low impedance load converts the electrical signal driven across the conductor as a current into a voltage for further processing.
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Rex T Baird from Bozeman, MT, age ~60 Get Report