Search

Reid E Tatge

from Sugar Land, TX
Age ~65
Get Report
Also known as:
Reid Pamela Tatge, Edmund Tatge Reid
Related to:
Martha W Miller, 63Kelley Pate, 56Alex TatgePamela K TatgePamela K Leavens, 64John W Tatge, 98Marilyn I Leavens, 84Annette M Tatge, 98T WardPamela K Tatge, 64Leonard J Leavens, 84Alex Tatge, 32
Connected to:
Beth R Tatge, 52Chad A Tatge, 53Eric Tatge, 84Julie K Tatge, 67Ray C Tatge, 66Candace Tatham, 68Cathy F Tatham, 62Daniel L Tatham, 80Daren C Tatham, 45Gary G Tatham, 73

Reid Tatge Phones & Addresses

  • Sugar Land, TX
  • Los Altos, CA
  • 1707 Copperwood Ct, Richmond, TX 77469 (281) 232-9466
  • Houston, TX
  • Missouri City, TX
  • Austin, TX

Work

Company: Texas instruments Position: Fellow

Education

Degree: Bachelors, Bachelor of Science School / High School: Purdue University 1977 to 1981 Specialities: Computer Science

Skills

Digital Signal Processors • Embedded Systems • Processors • Soc • Semiconductors • C • Arm • Debugging • Software Development • Embedded Software • Computer Architecture • Compilers • Compiler Optimization • Hardware Architecture • Microprocessors • Algorithms • Fpga • Firmware • Compiler Construction • Arm Architecture • Rtos • System on A Chip • Omap

Interests

Children

Industries

Computer Software

Resumes

Resumes

Reid Tatge Photo 1

Senior Staff Software Engineer And Technician Lead Manager

View page
Location:
P/O Box 17808, Sugar Land, TX
Industry:
Computer Software
Work:
Texas Instruments
Fellow
Texas Instruments - Houston, Texas Area Jan 2012 - 2012
DSP R&D Branch Manager for Programmable Processors Group
Texas Instruments - Houston, Texas Area 1981 - 2011
Director of TI's Compiler Development Group
Education:
Purdue University 1977 - 1981
Bachelors, Bachelor of Science, Computer Science
Skills:
Digital Signal Processors
Embedded Systems
Processors
Soc
Semiconductors
C
Arm
Debugging
Software Development
Embedded Software
Computer Architecture
Compilers
Compiler Optimization
Hardware Architecture
Microprocessors
Algorithms
Fpga
Firmware
Compiler Construction
Arm Architecture
Rtos
System on A Chip
Omap
Interests:
Children

Publications

Us Patents

Processor With Conditional Execution Of Every Instruction

View page
US Patent:
6374346, Apr 16, 2002
Filed:
Jan 23, 1998
Appl. No.:
09/012326
Inventors:
Natarajan Seshan - Houston TX
Reid E. Tatge - Richmond TX
Alan L. Davis - Sugarland TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 9302
US Classification:
712221
Abstract:
A general purpose microprocessor architecture enabling more efficient computations of a type in which Boolean operations and arithmetic operations conditioned on the results of the Boolean operations are interleaved. The microprocessor is provided with a plurality of general purpose registers (âGPRsâ )and an arithmetic logic unit (âALUâ ), capable of performing arithmetic operations and Boolean operations. The ALU has a first input ( ) and a second input ( ), and an output ( ), the first and second inputs receiving values stored in the GPRs. The output stores the results of the arithmetic logic unit operations in the GPRs. At least one of the GPRs is capable of receiving directly from the ALU a result of a Boolean operation. In one embodiment, at least one of the GPRs (PN)capable of receiving directly from the ALU a result of a Boolean operation is configured so as to cause the conditioning of an arithmetic operation of the ALU based on the value stored in the GPR.

Processor Integrated Circuit

View page
US Patent:
6411984, Jun 25, 2002
Filed:
May 1, 1998
Appl. No.:
09/071718
Inventors:
Jerald G. Leach - Houston TX
Laurence R. Simar - Richmond TX
Alan L. Davis - Houston TX
Reid E. Tatge - Richmond TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 1300
US Classification:
709200, 709237
Abstract:
A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data. Further included is an address generating unit connected to the storage circuit, the instruction register, and the address register responsive to the control signals from the instruction decode and control unit combining the initial address word from the address register and the address data from the displacement section to generate a storage circuit address. Other devices, systems and methods are also disclosed.

Processing Devices With Improved Addressing Capabilities Systems And Methods

View page
US Patent:
6625719, Sep 23, 2003
Filed:
Jun 14, 2002
Appl. No.:
10/172590
Inventors:
Jerald G. Leach - Houston TX
Laurence R. Simar - Richmond TX
Alan L. Davis - Houston TX
Reid E. Tatge - Richmond TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 1200
US Classification:
711220
Abstract:
A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data. Further included is an address generating unit connected to the storage circuit, the instruction register, and the address register responsive to the control signals from the instruction decode and control unit combining the initial address word from the address register and the address data from the displacement section to generate a storage circuit address. Other devices, systems and methods are also disclosed.

User Interface For Making Compiler Tradeoffs

View page
US Patent:
6718544, Apr 6, 2004
Filed:
Feb 22, 2000
Appl. No.:
09/510217
Inventors:
Jonathan F. Humphreys - Missouri City TX
Alan S. Ward - Sugarland TX
Reid E. Tatge - Richmond TX
David H. Bartley - Dallas TX
Paul C. Fuqua - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 945
US Classification:
717158, 717140, 717151, 717130
Abstract:
A user interface that allows a user to visually understand, inspect, and manipulate a compiled application program as a function of compiler options, such as, code size and speed, is provided.

Microprocessor With An Instruction Immediately Next To A Branch Instruction For Adding A Constant To A Program Counter

View page
US Patent:
6889320, May 3, 2005
Filed:
Oct 31, 2000
Appl. No.:
09/702462
Inventors:
Alan L. Davis - Sugarland TX, US
Richard H. Scales - Houston TX, US
Natarajan Seshan - Houston TX, US
Eric J. Stotzer - Houston TX, US
Reid E. Tatge - Richmond TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F009/42
US Classification:
712233
Abstract:
A data processing system with a microprocessor that has an instruction execution pipeline that includes fetch and decode stages and several functional execution units. Fetch packets contain a plurality of instruction words. Execution packets include a plurality of instruction words that can be executed in parallel by two or more execution units. An execution packet can span two or more fetch packets. An add (k) constant to program counter (ADDKPC) instruction is provided, such that a parameter specified by the ADDKPC instruction is combined with a value provided by a program counter of microprocessor. The ADDKPC instruction can also specify a number of delay slots after a branch instruction to be filled with virtual NOP instructions such that memory is not wasted with useless NOP instructions. An ADDKPC instruction can provide a relative address for use as a return address. A plurality of predicated ADDKPC instructions can provide a return address selected from a plurality of return addresses.

Method Of Generating Profile-Optimized Code

View page
US Patent:
6922829, Jul 26, 2005
Filed:
Jan 17, 2001
Appl. No.:
09/761152
Inventors:
Alan S. Ward - Sugarland TX, US
Reid E. Tatge - Richmond TX, US
Jonathan F. Humphreys - Missouri City TX, US
David H. Bartley - Dallas TX, US
Paul C. Fuqua - Dallas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F009/45
G06F009/44
US Classification:
717154, 717130
Abstract:
A method of generating profiled optimized code using user interface () that allows a user to visually understand, inspect, and manipulate a compiled application program as a function of compiler options, such as, code size and speed, is provided. A program () is compiled in a compiler () with two or more compiler options such as size and speed and the resulting executables () are profiled (). The results of the profiles () are analyed in a solver () for generating sets of useful solutions () wherein the sets have methods of compiling at the function level. The useful solutions () are displayed () at the user interface () to allow the user to visually understand, inspect and manipulate compiler options to select compiler options () for the program.

Register Allocation And Code Spilling Using Interference Graph Coloring

View page
US Patent:
7240344, Jul 3, 2007
Filed:
Aug 13, 2003
Appl. No.:
10/640549
Inventors:
Reid E. Tatge - Missouri City TX, US
Jonathan F. Humphreys - Missouri City TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 9/44
G06F 9/45
US Classification:
717159, 717131, 717132, 717133, 717154, 717155, 717157, 717158
Abstract:
An improved method is provided for performing register allocation in a compiler. This method determines the allocation of a plurality R of registers of a processor for use during the execution of a software program. The register allocation process is treated as a graph-coloring problem, such that an interference graph is constructed for the software program, the graph is simplified, and an R-coloring the interference graph to the extent possible is attempted. Then, spill code is inserted in the software program each for each uncolored node of the graph, a new interference graph is constructed, and the process is repeated. During the simplification process, nodes with degree greater than or equal to R are removed from the graph in an order dictated by a spill cost metric. During the coloring process, these same nodes are reinserted in the graph in an order dictated by reapplying the spill cost metric.

Method For Design Of Programmable Data Processors

View page
US Patent:
7886255, Feb 8, 2011
Filed:
Jan 22, 2008
Appl. No.:
12/017503
Inventors:
Reid E. Tatge - Missouri City TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G06F 17/50
US Classification:
716104, 716106, 716132, 703 16
Abstract:
A method of integrated circuit programmed data processor design includes selecting a benchmark application, selecting an initial set of architecture parameters, reconfiguring a compiler for the selected architecture parameters, compiling the benchmark, reconfiguring a data processor simulator to the selected architecture parameters, running the complied benchmark on the reconfigured simulator, automatically synthesizing an integrated circuit physical layout and evaluating performance of the selected architecture parameters against predetermined criteria. The method varies the selected architecture parameters upon failure to meet criteria until evaluation of the selected architecture parameters meets the criteria. The method selects a number of datapath clusters to avoid too many input/output ports in data registers.
Control profile
Reid E Tatge from Sugar Land, TX, age ~65 Get Report