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Ray W Cheng

from Danville, CA
Age ~81

Ray Cheng Phones & Addresses

  • 346 Newcastle Ln, Danville, CA 94506 (408) 262-5989
  • Concord, CA
  • San Ramon, CA
  • San Diego, CA
  • Milpitas, CA
  • San Jose, CA

Resumes

Resumes

Ray Cheng Photo 1

Experienced R&D / Aml / Mfg /Eng Senior Technician At Novellus System Inc

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Position:
Sr. Engineering Technician at Novellus System Inc
Location:
San Francisco Bay Area
Industry:
Semiconductors
Work:
Novellus System Inc since Jan 2010
Sr. Engineering Technician

Novellus System Inc Jan 1999 - Dec 2009
Technician V (Lead)

Aplex Group Jan 1997 - Jan 1999
Engineering Technician

Appliance Services Jan 1995 - Nov 1996
Owner

Techtronics Industries Jan 1986 - Jan 1992
Production/Product Engineer
Ray Cheng Photo 2

President, Black Pearl Transportation

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Position:
President at Black Pearl Transportation
Location:
San Francisco Bay Area
Industry:
Leisure, Travel & Tourism
Work:
Black Pearl Transportation since May 2004
President
Ray Cheng Photo 3

Principle Engineer At Trend Micro

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Position:
Principle Engineer at Trend Micro
Location:
San Francisco Bay Area
Industry:
Computer Software
Work:
Trend Micro - Cupertino, CA since May 2012
Principle Engineer

Yahoo! - Sunnyvale Feb 2010 - Apr 2012
Principle Engineer

Stark Technology Inc. Feb 2003 - Feb 2010
CTO

Sun Microsystems 1985 - 2003
Senior Staff Engineer
Education:
University of Illinois at Urbana-Champaign 1978 - 1983
Ph.D., Computer Science
Ray Cheng Photo 4

Ray Cheng

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Location:
United States
Ray Cheng Photo 5

Ray Cheng

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Location:
San Francisco Bay Area
Industry:
Information Technology and Services
Ray Cheng Photo 6

Design Professional

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Location:
San Francisco Bay Area
Industry:
Design
Work:
versatec 1970 - 1998
pcb designer
Ray Cheng Photo 7

Pcb Designer At Aptina

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Position:
PCB designer at Apertina
Location:
San Francisco Bay Area
Industry:
Computer Hardware
Work:
Apertina
PCB designer

adaptec 1996 - 2000
ray cheng

ltx 1996 - 2000
ray cheng

versatec 1980 - 2000
cowles

western microwave 1970 - 1976
ra

Business Records

Name / Title
Company / Classification
Phones & Addresses
Ray Cheng
Principal
R & K Service
Services-Misc
2544 Cedarwood Loop, San Ramon, CA 94582

Publications

Us Patents

Virtual Address Write Back Cache With Address Reassignment And Cache Block Flush

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US Patent:
58453253, Dec 1, 1998
Filed:
Apr 13, 1993
Appl. No.:
8/046476
Inventors:
William Van Loo - Palo Alto CA
John Watkins - Sunnyvale CA
Robert Garner - San Jose CA
William Joy - Palo Alto CA
Joseph Moran - Santa Clara CA
William Shannon - Los Altos CA
Ray Cheng - Cupertino CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
International Classification:
G06F 1516
G06F 1208
US Classification:
711135
Abstract:
Hardware and software improvements in workstations which utilize virtual addressing in multi-user operating systems with write back caches, including operating systems which allow each user to have multiple active processes. In virtual addressing, multi-user workstations, system performance may be improved significantly by including a virtual address write back cache as one of the system elements. Data protection and the reassignment of virtual addresses are supported within such a system as well. Multiple active processes, each with its own virtual address space, and an operating system shared by those processes in a manner which is invisible to user programs. Cache "Flush" logic is used to remove selected blocks from the virtual cache when virtual addresses are to be reassigned.

Alias Address Support

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US Patent:
51192900, Jun 2, 1992
Filed:
Jul 16, 1990
Appl. No.:
7/554186
Inventors:
William V. Loo - Palo Alto CA
John Watkins - Sunnyvale CA
Joseph Moran - Santa Clara CA
William Shannon - Los Altos CA
Ray Cheng - Cupertino CA
Assignee:
Sun Microsystems, Inc. - Mountain View CA
International Classification:
G06F 1208
US Classification:
395400
Abstract:
Improvements in workstations which utilizes virtual addressing in multi-user operating systems with write back caches, including operating systems which allow each user to have multiple active processes directed to the support of alias addresses, i. e. , two or more virtual addresses which map to the same physical address in real memory Specifically, alias addresses are created so that their low order address bits are identical, modulo the size of the cache (as a minimum) for user programs which use alias addresses generated by the kernel, or wholely within the kernel. For alias addresses in the operating system, rather than user programs, which cannot be made to match in their low order address bits, their pages are assigned as "Don't Cache" pages in the memory management unit (MMU) employed by workstations which utilize virtual addressing.
Ray W Cheng from Danville, CA, age ~81 Get Report