Ravi P Annavajjhala

6605984, Aug 12, 2003

Jan 2, 2002

10/038499

Ravi P. Annavajjhala - Folsom CA
Mary Frances Therese B. Yuvienco - Las Pinas, PH

Intel Corporation - Santa Clara CA

G05F 308

327536, 327535

Circuits reduce the ripple in charge pump output by staggering the times at which charge is drawn from the pump. In one embodiment, the outputs of a two-array high current pump are staggered by multiplexing two pairs of clock inputs, the second pair being 180 degrees out of phase with the first clock input pair. When an EEPROM is in a programming or erase algorithm, multiplexers switch the clock inputs to the second array, effectively inverting the input clock signals. After switching, the output from the second array is 180 degrees out of phase with the output from the first array. The peak-to-peak ripple in the charge pump output is thereby reduced to about 400 mV or less.

6836176, Dec 28, 2004

Jun 27, 2002

10/185419

Raymond W. Zeng - Folsom CA
Ravi P. Annavajjhala - Folsom CA
Mary Frances Therese B. Yuvienco - Las Pinas, PH

Intel Corporation - Santa Clara CA

G05F 1576

327535, 327544, 36518909

A charge pump control circuit may include a frequency synthesis device, a pump cell connected to the frequency synthesis device, and a feedforward circuit connected to the frequency synthesis device to selectively activate or deactivate the frequency synthesis device in response to a pump cell output signal.

6917554, Jul 12, 2005

Jul 24, 2003

10/626469

Ravi P. Annavajjhala - Folsom CA, US

Intel Corporation - Santa Clara CA

G11C007/00
H02H003/22

365226, 327534, 361111

A protection circuit that permits the use of thin oxide transistor devices. In one embodiment, the circuit is used to protect internal nodes of a flash EEPROM chip from a power pad voltage. A thin oxide device can be used to directly couple the power pad to an internal node of the flash chip. Optionally, thin oxide devices can also be used to set the steady state internal node voltage and a current source can be coupled to the node to bleed sub-threshold current. In yet another embodiment, a pull down circuit is coupled to the node to pull the node immediately down to a desired steady state voltage when the EEPROM algorithm is completed.

6947328, Sep 20, 2005

Dec 29, 2003

10/747802

Alec W. Smidt - Folsom CA, US
Andrew D. Proescholdt - Rancho Cordova CA, US
Boubekeur Benhamida - El Dorado Hills CA, US
Ravi Annavajjhala - Folsom CA, US

Intel Corporation - Santa Clara CA

G11C016/06

36518523, 36518524, 36518511

A high-speed voltage level shifter. A transistor () may be connected to high voltage (VPP) and may act as a source of a limited current to a first node (), and a driver () connected to the first node may provide a level-shifted output signal (VOUT) to a memory control input line of a memory cell (). A plurality of series-connected transistors (A–N) may be connected between a second node (A) and a circuit ground, each transistor may have an input connected to a corresponding control signal (VIN-A to VIN-N) from a control circuit (). A transistor () may be connected between the first node and the second node in a source-follower configuration and may have an input connected to a bias voltage (VBIAS) which may limit the voltage at node A, so transistors A–N may be low-voltage, high speed transistors.

7577024, Aug 18, 2009

May 25, 2007

11/807125

Richard E. Fackenthal - Carmichael CA, US
Ferdinando Bedeschi - Biassono, IT
Ravi Annavajjhala - Folsom CA, US
Giulio Casagrande - Vignate, IT

Intel Corporation - Santa Clara CA

G11C 11/00

365163, 365148, 36518519, 36518518, 36518503, 257 2, 257 3, 257 4, 257 5

A streaming programming mode may be implemented on user command in a phase change memory. In the streaming programming mode, accelerated programming may be achieved by ramping up to a voltage that it used for both reading and programming. Repeated programming operations may be streamed after one ramp up without ramping down the voltage on the memory cells between programming operations. This may save time. In addition, the memory may be read in between programming operations, again, without necessarily ramping down.

7802132, Sep 21, 2010

Aug 17, 2007

11/840421

Ravi Annavajjhala - Folsom CA, US
Brian A. Dargel - Folsom CA, US
Hiroyuki Kuwahara - Yokohama, JP
Touhid M. Raza - Cordova CA, US

Intel Corporation - Santa Clara CA

G06F 11/00

714 7, 711103, 711170

A novel technique to improve and extend endurance and reliability of a memory device utilizing multi-level cells is disclosed. As a memory device ages, it's reliability deteriorates. Prior to the memory device becoming completely unreliable, the memory device transitions from a multi-level cell operating mode to a reduced capacity operating mode. When operating in the multi-level cell mode, the memory system stores multiple bits per cell. The memory system stores fewer bits per cell when operating in the reduced capacity. The transition between modes is achieved by setting all bits of a particular memory page to a specific value, for example, either a logic “1” or a logic “0. ”.

7885099, Feb 8, 2011

Sep 18, 2007

11/901493

Richard E. Fackenthal - Carmichael CA, US
Ferdinando Bedeschi - Milan, IT
Meenatchi Jagasivamani - Fairfield CA, US
Ravi Annavajjhala - Folsom CA, US
Enzo M. Donze - Agrate Brianza, IT

Intel Corporation - Santa Clara CA

G11C 11/00

365163, 365148, 977754

The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.

8018763, Sep 13, 2011

Dec 9, 2010

12/963717

Richard E. Fackenthal - Carmichael CA, US
Ferdinando Bedeschi - Biassono, IT
Meenatchi Jagasivamani - Fairfield CA, US
Ravi Annavajjhala - Folsom CA, US
Enzo M. Donze - Agrate Brianza, IT

Intel Corporation - Santa Clara CA

G11C 11/00

365163, 365148, 977754

The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.