Search

Randall Pak Phones & Addresses

  • Euless, TX
  • Hurst, TX
  • Aiea, HI
  • Fort Worth, TX

Publications

Us Patents

Post Metal Gate Vt Adjust Etch Clean

View page
US Patent:
7785957, Aug 31, 2010
Filed:
Dec 26, 2008
Appl. No.:
12/344422
Inventors:
Brian K. Kirkpatrick - Allen TX, US
Jinhan Choi - Frisco TX, US
Randall W. Pak - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/00
US Classification:
438229, 438592, 438906
Abstract:
A method for fabricating a CMOS integrated circuit (IC) includes providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the semiconductor surface followed by forming at least a first metal including layer on the gate dielectric layer. A polysilicon or amorphous silicon layer is formed on the first metal including layer to form an intermediate gate electrode stack. A masking pattern is formed on the intermediate gate electrode stack. The polysilicon or amorphous silicon layer is dry etched using the masking pattern to define a patterned intermediate gate electrode stack over the NMOS or PMOS regions, wherein the dry etching stops on a portion of the first metal comprising layer. The masking pattern is removed using a first post etch clean for stripping the masking pattern. A multi-step solution cleaning sequence is used after the removing step and includes a first wet clean including sulfuric acid and a fluoride, and a second wet clean after the first wet clean including a fluoride.

Post Plasma Clean Process For A Hardmask

View page
US Patent:
20050090115, Apr 28, 2005
Filed:
Oct 24, 2003
Appl. No.:
10/692609
Inventors:
Brian Kirkpatrick - Allen TX, US
Clint Montgomery - Coppell TX, US
Brian Trentman - Sherman TX, US
Randall Pak - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L021/302
US Classification:
438706000
Abstract:
The present invention provides a process of manufacturing a semiconductor device that comprises a process of manufacturing a semiconductor device that includes plasma etching through a patterned hardmask layer located over a semiconductor substrate wherein the plasma etching forms a modified layer on the hardmask layer , and removing at least a substantial portion of the modified layer by exposing the modified layer to a post plasma clean process.
Randall Pak from Euless, TX, age ~48 Get Report