Rameshkumar G Illikkal

7293108, Nov 6, 2007

Mar 15, 2001

09/811011

Ulhas S. Warrier - Beaverton OR, US
Saul Lewites - Hillsboro OR, US
Rameshkumar G. Illikkal - Portland OR, US
Ramanan Ganesan - Hillsboro OR, US

Intel Corporation - Santa Clara CA

G06F 15/16

709249, 709202, 709230

A first machine communicates with a second machine, using a protocol that sends the first machine's network configuration data in application data sent to the second machine, through a translating access point which translates network traffic from the first machine so as to originate from the access point. A network configuration server provides to the first machine network configuration data not subject to translation by the access point, which is sent to the second machine in the application data. The second machine communicates with the provided network configuration, and this communication is in turn made available to the first machine.

7346680, Mar 18, 2008

Sep 22, 2003

10/667691

Rameshkumar G. Illikkal - Portland OR, US
Gregory D. Cummings - Portland OR, US

Intel Corporation - Santa Clara CA

G06F 15/173
G06F 15/16

709224, 709223, 709250

According to some embodiments, a protocol control block is speculatively pre-fetched from an external memory unit.

7490191, Feb 10, 2009

Sep 22, 2006

11/525980

Rameshkumar G. Illikkal - Portland OR, US
Donald K. Newell - Portland OR, US
Ravishankar Iyer - Portland OR, US
Srihari Makineni - Portland OR, US

Intel Corporation - Santa Clara CA

G06F 12/10

711 6, 711203, 711207

Embodiments of apparatuses, methods, and systems for sharing information between guests in a virtual machine environment are disclosed. In one embodiment, an apparatus includes virtual machine control logic, an execution unit, and a memory management unit. The virtual machine control logic is to transfer control of the apparatus among a host and its guests. The execution unit is to execute an instruction to copy information from a virtual memory address in one guest's virtual address space to a virtual memory address in another guest's virtual address space. The memory management unit is to translate the virtual memory addresses to physical memory addresses.

7627674, Dec 1, 2009

Jan 18, 2008

12/016446

Rameshkumar G. Illikkal - Portland OR, US
Gregory D. Cummings - Portland OR, US

Intel Corporation - Santa Clara CA

G06F 15/173
G06F 15/16

709224, 709232, 709250

According to some embodiments, protocol control information is speculatively pre-fetched from an external memory unit. For example, a processing engine may speculate, based on a receive packet, a connection that will subsequently have a send packet to be processed in accordance with a protocol. The processing engine may also dynamically calculate a time when protocol control information, associated with the speculated connection, is to be pre-fetched from an external memory unit (e. g. , the time may be calculated in accordance with an estimated processing time associated with the receive packet and an estimated latency time associated with pre-fetching the protocol control information from the external memory unit). The protocol control information associated with the connection may then be pre-fetched from the external memory unit in accordance with the dynamically calculated time.

7668306, Feb 23, 2010

Mar 8, 2002

10/095138

Carl R. Strathmeyer - Reading MA, US
Hugh P. Mercer - Hollis NH, US
Donald K. Finnie - Reading, GB
Rameshkumar G. Illikkal - Portland OR, US
Bounthavivone K. Phomsopha - Portland OR, US

Intel Corporation - Santa Clara CA

H04M 7/00
H04L 12/66

379219, 370352

Described herein is a method and apparatus for connecting packet telephony calls between secure networks and non-secure networks.

7937534, May 3, 2011

Dec 30, 2005

11/323262

Rajesh Sankaran Madukkarumukumana - Portland OR, US
Sridhar Muthrasanallur - Puyallup WA, US
Ramakrishna Huggahalli - Scottsdale AZ, US
Rameshkumar G. Illikkal - Portland OR, US

G06F 13/368

711138, 711E12052

Embodiments of an apparatus, method, and system for encoding direct cache access transactions based on a memory access data structure are disclosed. In one embodiment, an apparatus includes memory access logic and transaction logic. The memory access logic is to determine whether to allow a memory access based on a memory access data structure. The transaction logic is to assign direct cache access attributes to a transaction based on the memory access data structure.

7991956, Aug 2, 2011

Jun 27, 2007

11/823325

Rameshkumar Illikkal - Portland OR, US
Ravishankar Iyer - Portland OR, US
Li Zhao - Beaverton OR, US
Donald Newell - Portland OR, US
Carl Lebsack - Ames IA, US
Quinn A. Jacobson - Sunnyvale CA, US
Suresh Srinivas - Portland OR, US
Mingqiu Sun - Beaverton OR, US

Intel Corporation - Santa Clara CA

G06F 12/00

711118, 711133, 711141, 711E12016, 711E12026

In one embodiment, the present invention includes a method for associating a first identifier with data stored by a first agent in a cache line of a cache to indicate the identity of the first agent, and storing the first identifier with the data in the cache line and updating at least one of a plurality of counters associated with the first agent in a metadata storage in the cache, where the counter includes information regarding inter-agent interaction with respect to the cache line. Other embodiments are described and claimed.

8392657, Mar 5, 2013

Oct 9, 2009

12/587670

Li Zhao - Beaverton OR, US
Ravishankar Iyer - Portland OR, US
Rameshkumar G. Illikkal - Portland OR, US
Erik G. Hallnor - Beaverton OR, US
Martin G. Dixon - Portland OR, US
Donald K. Newell - Portland OR, US

Intel Corporation - Santa Clara CA

G06F 12/00
G06F 13/00
G06F 13/28

711121, 711122

An apparatus, method, and system are disclosed. In one embodiment the apparatus includes a cache memory, which a number of sets. Each of the sets in the cache memory have several cache lines. The apparatus also includes at least one process resource table. The process resource table maintains a cache line occupancy count of a number of cache lines. Specifically, the cache line occupancy count for each cache line describes the number of cache lines in the cache storing information utilized by a process running on a computer system. Additionally, the process resource table stores the occupancy count of less cache lines than the total number of cache lines in the cache memory.