Search

Raman S Thiara

from San Jose, CA
Age ~53
Get Report
Also known as:
Raman Singh Thiara, Raman Te Thiara, Raman Thiara Singh
Phone and address:
1601 Montellano Ct, San Jose, CA 95120
(408) 440-1071
Related to:
Navneet K Toor, 39Satpal ThiaraRavinder Sood, 68Paramjit Mahal, 69Joyvinder Singh, 50
Connected to:
Harnek S Thiara, 68Mandeep K Thiara, 56Teresita Thiara, 79Jacob A Thias, 40Marcia H Thias, 85Nancy M Thias, 58Dalton J Thibadeau, 34Catherine M Thibaudeau, 79Deborah A Thibaudeau, 70Eric T Thibaud, 63

Raman Thiara Phones & Addresses

  • 1601 Montellano Ct, San Jose, CA 95120 (408) 440-1071
  • Cordova, TN
  • Little Rock, AR
  • Memphis, TN
  • Lilburn, GA
  • Conyers, GA
  • Sunnyvale, CA
  • Santa Clara, CA
  • Los Angeles, CA
  • 1601 Monteval Ct, San Jose, CA 95120

Work

Company: Apple Jan 2015 Position: Wireless architect

Education

Degree: Masters, Master of Science In Electrical Engineering School / High School: University of California, Los Angeles 1996 to 1998 Specialities: Electrical Engineering

Skills

Cmos • Ic • Semiconductors • Mixed Signal • Analog Circuit Design • Vco • Pll • Rf • Circuit Design • Analog • Simulations • Rf Design • Matlab • Analog Design • Simulation • Serdes

Languages

English

Industries

Consumer Electronics

Resumes

Resumes

Raman Thiara Photo 1

Wireless Architect

View page
Location:
1601 Montellano Ct, San Jose, CA 95120
Industry:
Consumer Electronics
Work:
Apple
Wireless Architect
Apple Jul 2010 - Dec 2014
Design Manager
Siport Aug 2006 - Jul 2010
Director of Rf and Mixed-Signal Ic Design
Maxim Integrated Aug 1999 - Aug 2006
Rf Design Group Leader
Intel Corporation 2001 - 2003
Senior Analog and Mixed-Signal Ic Designer
Education:
University of California, Los Angeles 1996 - 1998
Masters, Master of Science In Electrical Engineering, Electrical Engineering University of California, Davis 1990 - 1994
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Cmos
Ic
Semiconductors
Mixed Signal
Analog Circuit Design
Vco
Pll
Rf
Circuit Design
Analog
Simulations
Rf Design
Matlab
Analog Design
Simulation
Serdes
Languages:
English

Publications

Us Patents

Charge Pump Architecture

View page
US Patent:
20040119513, Jun 24, 2004
Filed:
Dec 20, 2002
Appl. No.:
10/325051
Inventors:
Raman Thiara - Sunnyvale CA, US
International Classification:
H03L007/06
US Classification:
327/157000
Abstract:
According to some embodiments, a charge pump includes a first transistor to steer an amount of current to a second transistor coupled to the first transistor in a first folded cascode arrangement and to a current mirror to sink substantially the amount of current from a load, and a third transistor to steer the amount of current to a fourth transistor coupled to the third transistor in a second folded cascode arrangement to source substantially the amount of current to the load.

Methods And Architectures For Secure Ranging

View page
US Patent:
20220225267, Jul 14, 2022
Filed:
Jan 24, 2022
Appl. No.:
17/582785
Inventors:
- Cupertino CA, US
Alejandro J. MARQUEZ - Sunnyvale CA, US
Timothy R. PAASKE - San Jose CA, US
Indranil S. SEN - Cupertino CA, US
Herve SIBERT - San Francisco CA, US
Yannick L. SIERRA - San Francisco CA, US
Raman S. THIARA - San Jose CA, US
International Classification:
H04W 64/00
H04W 12/03
H04W 12/033
H04W 12/041
H04W 12/062
H04W 12/63
H04W 12/065
H04W 12/069
H04W 12/0431
H04W 12/0433
H04W 12/0471
H04W 76/10
H04L 9/32
H04L 9/40
H04W 12/02
H04W 12/04
H04W 12/06
Abstract:
A secure ranging system can use a secure processing system to deliver one or more ranging keys to a ranging radio on a device, and the ranging radio can derive locally at the system ranging codes based on the ranging keys. A deterministic random number generator can derive the ranging codes using the ranging key and one or more session parameters, and each device (e.g. a cellular telephone and another device) can independently derive the ranging codes and derive them contemporaneously with their use in ranging operations.

Electronic Device Functionality In Low Power Mode

View page
US Patent:
20230061200, Mar 2, 2023
Filed:
Sep 1, 2021
Appl. No.:
17/464482
Inventors:
- Cupertino CA, US
Arun Unkn - Cupertino CA, US
Andrew C. Chang - Sunnyvale CA, US
Sriram Hariharan - San Jose CA, US
Robert W. Brumley - San Jose CA, US
Raman S. Thiara - San Jose CA, US
International Classification:
G06F 1/3206
G06F 13/42
H04B 17/318
Abstract:
Embodiments disclosed herein relate to reducing a power consumption of an electronic device while maintaining some functionality of the electronic device while the electronic device is in a low power mode. The device may be in the low power mode due to a battery level being below a threshold. If the battery level is below the threshold, the electronic device may enter the low power mode. However, before entering the low power mode, some functionality of an application processor may be transferred to a communication controller. Once the functionality is transferred, the application processor may be disabled to reduce power consumption while maintaining functionality of the application processor. The electronic device may also utilize various communication protocols to communicate with a peripheral device. Even though the electronic device may be in the low power mode, the communication controller may be used to cause the peripheral device to perform various actions.

Methods And Architectures For Secure Ranging

View page
US Patent:
20190116619, Apr 18, 2019
Filed:
Apr 14, 2017
Appl. No.:
16/090007
Inventors:
- Cupertino CA, US
Alejandro J. MARQUEZ - Sunnyvale CA, US
Timothy R. PAASKE - San Jose CA, US
Indranil S. SEN - Cupertino CA, US
Herve SIBERT - San Francisco CA, US
Yannick L. SIERRA - San Francisco CA, US
Raman S. THIARA - San Jose CA, US
International Classification:
H04W 76/10
H04W 64/00
H04W 12/02
Abstract:
A secure ranging system can use a secure processing system to deliver one or more ranging keys to a ranging radio on a device, and the ranging radio can derive locally at the system ranging codes based on the ranging keys. A deterministic random number generator can derive the ranging codes using the ranging key and one or more session parameters, and each device (e.g. a cellular telephone and another device) can independently derive the ranging codes and derive them contemporaneously with their use in ranging operations.

Mitigation Of Power Supply Disturbance For Wired-Line Transmitters

View page
US Patent:
20160062430, Mar 3, 2016
Filed:
Aug 28, 2014
Appl. No.:
14/471759
Inventors:
- Cupertino CA, US
Raman S. Thiara - San Jose CA, US
Shingo Hatanaka - San Jose CA, US
International Classification:
G06F 1/26
H04L 7/08
Abstract:
A wired-line transmitter may include architecture that provides control of the current profile during power-up and/or power-down of the transmitter. The current profile may include a sloped ramp up during power-up and/or a sloped ramp down during power-down. The sloped ramps of the current profile mitigate supply bouncing during power-up and/or power-down. Individual enable signals may be derived from an enable signal provided to the transmitter. These individual enable signals may be provided (or turned off) in a time delayed (e.g., staggered) manner to provide the sloped ramps for the current profile.

Method And Apparatus For Power Glitch Detection In Integrated Circuits

View page
US Patent:
20150015283, Jan 15, 2015
Filed:
Jul 10, 2013
Appl. No.:
13/938901
Inventors:
- Cupertino CA, US
Patrick D. McNamara - San Francisco CA, US
Kwang M. Lee - Saratoga CA, US
Meng C. Chong - Milpitas CA, US
Geertjan Joordens - Sunnyvale CA, US
Raman S. Thiara - San Jose CA, US
Anh T. Hoang - Fremont CA, US
John P. Gonzalez - San Jose CA, US
International Classification:
G01R 31/319
US Classification:
32475001
Abstract:
A method and apparatus for power glitch detection in IC's is disclosed. In one embodiment, a method includes a detection circuit in an IC detecting a voltage transient wherein a value of a supply voltage has at least momentarily fallen below a reference voltage value. Responsive thereto, the detection circuit may cause a logic value to be stored in a register indicating that the detection circuit has detected the supply voltage falling below the reference voltage. The IC may include a number of detection circuits coupled to the register, each of which may provide a corresponding indication of detecting the supply voltage falling below the reference voltage. The detection circuits may be placed at different locations, and thus reading the register may yield information indicating the locations where, if any, such voltage transients occurred.

Clock Generation Using Fixed Dividers And Multiplex Circuits

View page
US Patent:
20140340130, Nov 20, 2014
Filed:
May 14, 2013
Appl. No.:
13/893926
Inventors:
- Cupertino CA, US
Raman S. Thiara - San Jose CA, US
Shane J. Keil - San Jose CA, US
Timothy J. Millet - Mountain View CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
H03K 3/02
US Classification:
327115
Abstract:
Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.

Low Power Display Port With Arbitrary Link Clock Frequency

View page
US Patent:
20140168234, Jun 19, 2014
Filed:
Dec 18, 2012
Appl. No.:
13/718142
Inventors:
- Cupertino CA, US
Geertjan Joordens - Sunnyvale CA, US
Moon Jung Kim - Cupertino CA, US
Raman S. Thiara - San Jose CA, US
Assignee:
APPLE INC. - Cupertino CA
International Classification:
G06T 1/20
US Classification:
345520
Abstract:
Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The source processor may be operable to select a frequency from a continuous range of frequencies, and transmit data to the sink processor at the selected frequency. A phase lock circuit may be included in the sink processor. The phase lock circuit may be configured to generate a signal at the selected frequency dependent upon the transmitted data. The generated signal may be in phase with the transmitted data.
Control profile
Raman S Thiara from San Jose, CA, age ~53 Get Report