Ralph G Oberhuber

7541872, Jun 2, 2009

Dec 21, 2007

11/962296

Ralph Oberhuber - Dallas TX, US

Texas Instruments Incorporated - Dallas TX

H03F 3/45

330261, 330257, 330297, 330296

A multi-stage circuit has a first stage powered by the output voltage of a next stage. A current source within the first stage provides a tail current for a differential amplifier within the first stage. When the first stage has an operating voltage high enough for proper operation, this tail current is at a nominal level; if the voltage is too low for proper operation of the first stage, the tail current is below this nominal level. A comparator, which has one input coupled to a node within this current source, a second input coupled to a threshold voltage, and an output coupled to a control node within the next stage, provides an output indicative of whether or not the tail current is substantially at its nominal level. If tail current is too low, the comparator provides a forcing signal to the control node of the next stage which causes the output of the next stage to be at a substantially nominal level regardless of the voltage at its input, thus providing a suitably high voltage for the first stage to begin normal operation. When the tail current reaches its nominal level, the comparator output changes state to one which has little or no effect on the output voltage of the second stage, and normal operation of the overall circuit begins.

7696909, Apr 13, 2010

Aug 23, 2006

11/509107

Ralph Oberhuber - Plano TX, US

Texas Instruments Incorporated - Dallas TX

H03M 1/06

341119, 327307, 327512, 327513

An apparatus for adjusting a first signal with respect to a second signal includes: (a) A first converter receiving the first signal and employing n first converting elements for digitally converting the first signal to at least one first signal element. (b) A second converter coupled with an output, receiving the second signal and employing n second converting elements for digitally converting the second signal to a second representative signal presented at the output. (c) An adjusting element coupled with each of selected of the first converting elements. Each adjusting element is coupled with the output and cooperates with the connected selected element to present a corrected signal element to the output. The output presents an aggregate output signal including contributions from the second representative signal and each corrected signal element. Adjusting is effected by altering at least one corrected first signal element presented to the output.

7710190, May 4, 2010

Aug 10, 2006

11/502822

Ralph Oberhuber - Plano TX, US

Texas Instruments Incorporated - Dallas TX

H03L 5/00
H01L 35/00

327512, 327513, 327539

An apparatus for compensating temperature changes in a temperature associated with a compensated device includes: (a) An input circuit having a first input locus for receiving a temperature-indicating signal and a second input locus for receiving a sign-indicating signal. The temperature-indicating signal indicates magnitude of the temperature. The sign-indicating signal indicates a first sign when a control signal is greater than a predetermined value and indicates a second sign when the control signal is less than the predetermined value. (b) A signal processing circuit coupled with the input circuit and with the host device for presenting a substantially a zero value temperature-compensating signal when the ambient temperature is at a predetermined level, and for presenting the temperature-compensating signal substantially opposite in polarity with substantially equal magnitude as the temperature-indicating signal received at the first input locus when the ambient temperature is not at the predetermined level.

7796060, Sep 14, 2010

Aug 7, 2008

12/188014

Ralph G. Oberhuber - Plano TX, US
Timothy V. Kalthoff - Tucson AZ, US

Texas Instruments Incorporated - Dallas TX

H03M 13/00

341 94, 341118

Circuits and methods to minimize nonlinearity errors in interpolating circuits are described herein. A disclosed example circuit comprises first and second voltage-current converter circuits, each including a first transistor and a second transistor, each having a first electrode configured to receive a signal generated by a corresponding current source, a first current source providing a signal to the first voltage-converter circuit and comprising a first error correction circuit to minimize integral nonlinearity error in the interpolation circuit by setting a first current through the first current source to operate the first voltage-converter circuit in a nominal linear operating mode, and a second current source providing a signal to the second voltage-converter circuit and comprising a second error correction circuit to minimize integral nonlinearity error in the interpolation circuit by setting a second current through the second current source to operate the second voltage-converter circuit in the nominal linear operating mode.

8514120, Aug 20, 2013

Nov 8, 2011

13/291853

Ralph G. Oberhuber - Plano TX, US
Tsedeniya A. Abraham - Dallas TX, US
Mark Shill - Tucson AZ, US

Texas Instruments Incorporated - Dallas TX

H03M 1/66

341144, 341154

An apparatus is provided that comprises resistors, a first set of switches, and a second set of switches. The resistors are arranged in an array having columns and rows, where the number of resistors is an integer multiple of the number of columns or rows. The resistors are coupled together in a skip-K pattern. Each switch from the first and second sets of switches is coupled to the resistor string, and the first and second sets of switches are each arranged in a sequence and are offset from one another by an offset value. The first and second sets of switches are arranged along the periphery of the array such that each switch from the first set of switches is located in proximity to and is associated with the same row or the same column as its corresponding switch in the sequence from the second set of switches.

8624661, Jan 7, 2014

Dec 21, 2007

11/962251

Ralph Oberhuber - Plano TX, US
Keith Brouse - Murphy TX, US

Texas Instruments Incorporated - Dallas TX

G06G 7/12

327362

A non-linear correction current ICTAT (current complementary to the square of absolute temperature) is generated from a current IPTAT (current proportional to absolute temperature) and a current ICTAT (current complementary to absolute temperature), both modified in a circuit having a topology and components which capitalize on the logarithmic relationship between transistor collector current and base-emitter voltage. The resulting ICTAT current (current complementary to the square of absolute temperature) is injected into a node of a bandgap reference circuit to compensate for non-linear temperature effects on output voltage. A more general correction circuit generates both IPTAT and ICTAT, and applies each to a respective multiplier which, in a preferred embodiment, is a current DAC configured as a multiplier. Control inputs CTL and CTL to respective multipliers set the amplitudes of the modified IPTAT and ICTAT output currents, which are then summed to generate the compensating current Icomp which is injected to the appropriate node in the bandgap reference circuit as described above. By adjusting the relative amplitudes of the IPTAT and ICTAT currents, a wide range of compensating current versus voltage curves is produced, allowing the optimization of a wide range of bandgap reference circuits.

20080290945, Nov 27, 2008

May 21, 2007

11/804866

Vadim V. Ivanov - Tucson AZ, US
Ralph G. Oberhuber - Plano TX, US

H03F 3/18

330264, 330263

A class AB output stage includes first (M) and a second (M) output transistors having sources coupled to first (V) and second reference voltages, respectively, drains coupled to an output (), and gates coupled to first (A) and second (A) conductors, respectively. Portions of first (I) and a second (I) input currents are sourced via a first input conductor () and a second input conductor (), respectively, into and from sources of first (M) and second (M) transistors, respectively. Gates of the first (M) and second (M) transistors are coupled to the first and second conductors, respectively. First (V) and second (V) bias voltages are applied to gates of third (M) and fourth (M) transistors respectively, having sources coupled to the first and second input conductors, respectively, and drains coupled to the second conductor.