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Rajit Manohar

from New Haven, CT
Age ~52
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Also known as:
Rajit Newberry
Phone and address:
244 Livingston St, New Haven, CT 06511
Related to:
Natalie M Casey, 45Shaun H Bone, 72Todd Greathouse, 49Dara M Newberry, 49Deirdre M Newberry, 52Dara M Nenberry, 49A O Newberry Rd, 84Patricia A NewberryPatricia A Newberry, 80
Connected to:
Adeline Manohar, 35Amy L Manoharan, 44Arun Manoharan, 49Aruna C Manohar, 38Balamurugan Manoharan, 42Chanel C Manohar, 65Chitra F Manohar, 65David K Manoharan, 39Debra V Manoharan, 69Janaki Manoharan, 36

Rajit Manohar Phones & Addresses

  • 244 Livingston St, New Haven, CT 06511
  • New York, NY
  • 427 Seneca St, Ithaca, NY 14850 (607) 256-1884
  • 4 Wildflower Dr, Ithaca, NY 14850 (607) 275-0604
  • 4D Wildflower Dr, Ithaca, NY 14850
  • 700 Stewart Ave, Ithaca, NY 14850 (607) 256-7396
  • Pasadena, CA
  • 427 E Seneca St, Ithaca, NY 14850

Work

Company: Yale university Jan 2017 Position: John c malone professor of electrical engineering and computer science

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Caltech 1995 to 1998 Specialities: Computer Science

Skills

Computer Science • Algorithms • Research • Simulations • Machine Learning • Vlsi • Programming • Parallel Computing • Embedded Systems

Emails

r***[email protected]

Industries

Semiconductors

Resumes

Resumes

Rajit Manohar Photo 1

John C Malone Professor Of Electrical Engineering And Computer Science

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Location:
111 8Th Ave, New York, NY 10011
Industry:
Semiconductors
Work:
Yale University
John C Malone Professor of Electrical Engineering and Computer Science
Cornell University Jul 2010 - Dec 2016
Professor
Cornell Tech Jul 2012 - Dec 2016
Professor
Cornell Tech Jan 2015 - Apr 2015
Associate Dean For Research
Cornell Tech Nov 2012 - Dec 2014
Associate Dean For Academic Affairs
Education:
Caltech 1995 - 1998
Doctorates, Doctor of Philosophy, Computer Science Caltech 1992 - 1994
Master of Science, Masters, Bachelors, Bachelor of Science, Applied Science, Computer Science, Engineering Indian Institute of Technology, Bombay 1990 - 1992
Skills:
Computer Science
Algorithms
Research
Simulations
Machine Learning
Vlsi
Programming
Parallel Computing
Embedded Systems

Business Records

Name / Title
Company / Classification
Phones & Addresses
Rajit Manohar
Branch Manager
Achronix Semiconductor Corporation
Mfg Semiconductors & Related Devices
95 Brown Rd, Ithaca, NY 14850
(607) 821-1751

Publications

Us Patents

Method And Apparatus For A Failure-Free Synchronizer

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US Patent:
6690203, Feb 10, 2004
Filed:
Dec 28, 2001
Appl. No.:
10/033176
Inventors:
Rajit Manohar - Ithaca NY
Alain J. Martin - Pasadena CA
Assignee:
California Institute of Technology - Pasadena CA
International Classification:
H03K 1900
US Classification:
326 94, 327 22, 327198, 327 23
Abstract:
Unlike prior art synchronizers and asynchronous arbiters that produce glitches in their outputs, the present invention provides a failure-free synchronizer that can sample an arbitrary and unstable inputs while maintaining zero probability of system failure. In particular, the invention addresses the synchronization failure problem and the lack of a metastable state in prior art synchronizers. Prior attempts have shown that the conditions re and a to hold the values re.

Programmable Asynchronous Pipeline Arrays

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US Patent:
7157934, Jan 2, 2007
Filed:
Aug 19, 2004
Appl. No.:
10/921349
Inventors:
John R. Teifel - Albuquerque NM, US
Rajit Manohar - Ithaca NY, US
Assignee:
Cornell Research Foundation, Inc. - Ithaca NY
International Classification:
H03K 19/173
US Classification:
326 38, 326 41, 326 46, 708490
Abstract:
High-performance, highly pipelined asynchronous FPGAs employ a very fine-grain pipelined logic block and routing interconnect architecture. These FPGAs, which do not use a clock to sequence computations, automatically “self-pipeline” their logic without the designer needing to be explicitly aware of all pipelining details. The FPGAs include arrays of logic blocks or cells that include function units, conditional units and other elements, each of which is constructed using basic asynchronous pipeline stages, such as a weak condition half buffer and a precharge half buffer.

Self-Timed Thermally-Aware Circuits And Methods Of Use Thereof

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US Patent:
7411436, Aug 12, 2008
Filed:
Feb 28, 2006
Appl. No.:
11/365567
Inventors:
David Fang - Ithaca NY, US
Filipp Akopyan - Ithaca NY, US
Rajit Manohar - Ithaca NY, US
Assignee:
Cornell REsearch Foundation, Inc. - Ithaca NY
International Classification:
H03H 11/26
US Classification:
327262, 327513
Abstract:
Apparatus and methods for regulating gate delays of synchronous and asynchronous digital circuits. Thermally-sensitive circuits include, generally, temperature sensitive voltage sources outputting a voltage signal indicative of the temperature of the digital circuit, where the voltage signal reflects non-linear temperature sensitivity above a predetermined threshold temperature, and delay mechanisms receiving said temperature sensitive voltage signal(s) as input and being configured to automatically continuously modulate the speed of signal propagation through the circuit in response to said voltage signal, thereby causing circuit elements within the circuits to switch less frequently and consequently causing the circuit elements to generate less heat with increasing circuit temperature.

Asynchronous Analog-To-Digital Converter And Method

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US Patent:
7466258, Dec 16, 2008
Filed:
Oct 10, 2006
Appl. No.:
11/545228
Inventors:
Filipp Akopyan - Ithaca NY, US
Alyssa Apsel - Ithaca NY, US
Rajit Manohar - Ithaca NY, US
Assignee:
Cornell Research Foundation, INc. - Ithaca NY
International Classification:
H03M 1/12
US Classification:
341155, 341159
Abstract:
A method and apparatus for converting an analog input signal to a digital output signal, provide for simultaneously comparing the input signal to a sequential multiplicity of reference values representing a range of values of the input signal, and asynchronously processing digital results from simultaneous comparison to produce a digital representation of level crossings of the input signal with respect to the multiplicity of reference values.

Fault Tolerant Asynchronous Circuits

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US Patent:
7504851, Mar 17, 2009
Filed:
Apr 25, 2007
Appl. No.:
11/740180
Inventors:
Rajit Manohar - Ithaca NY, US
Clinton W. Kelly - Ithaca NY, US
Assignee:
Achronix Semiconductor Corporation - San Jose CA
International Classification:
H03K 19/003
US Classification:
326 9, 326 10, 326 14, 326 15
Abstract:
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.

Fault Tolerant Asynchronous Circuits

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US Patent:
7505304, Mar 17, 2009
Filed:
Apr 25, 2007
Appl. No.:
11/740168
Inventors:
Rajit Manohar - Ithaca NY, US
Clinton W. Kelly - Ithaca NY, US
Assignee:
Achronix Semiconductor Corporation - San Jose CA
International Classification:
G11C 11/00
H03K 19/003
US Classification:
365154, 365156, 326 9, 326 12
Abstract:
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.

Event-Synchronization Protocol For Parallel Simulation Of Large-Scale Wireless Networks

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US Patent:
7564809, Jul 21, 2009
Filed:
May 6, 2005
Appl. No.:
11/123233
Inventors:
Rajit Manohar - Ithaca NY, US
Clint Kelly - Ithaca NY, US
Assignee:
Cornell Research Foundation, Inc. - Ithaca NY
International Classification:
H04B 7/00
US Classification:
370310
Abstract:
An event synchronization protocol called time-based synchronization (TBS) is employed to control operation of a network simulation. In TBS, processors in the simulated network execute events based on comparisons between timestamps for each event and a value generated by a time tracking device in the processor. In this manner, event execution is not dependent on other processes in the network and the simulation can actually be carried out at speeds faster than real time. A multiprocessor network is specially designed to execute TBS-based simulations.

Systems And Methods For Performing Automated Conversion Of Representations Of Synchronous Circuit Designs To And From Representations Of Asynchronous Circuit Designs

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US Patent:
7610567, Oct 27, 2009
Filed:
Apr 25, 2007
Appl. No.:
11/740184
Inventors:
Rajit Manohar - Ithaca NY, US
Assignee:
Achronix Semiconductor Corporation - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 3, 716 6
Abstract:
Methods and systems automate an approach to provide a way to convert a circuit design from a synchronous representation to an asynchronous representation without any designer or user interaction or redesign of the synchronous circuit. An optimized, automated, non-Interactive conversion of representations of synchronous circuit designs to and from representations of asynchronous circuit designs, facilitating traditional electronic design automation (EDA) tools to process and manipulate asynchronous designs while allowing synchronous designs to be implemented using asynchronous hardware solutions. The invention also facilitates feedback to synchronous design tools in synchronous representation for optimization and iteration of the design process by engineers, eliminating the need for engineers to be aware of the underlying asynchronous architecture of the underlying hardware implementation.
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Rajit Manohar from New Haven, CT, age ~52 Get Report