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Rahul Nimaiyar

from Sunnyvale, CA
Age ~50
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Also known as:
Rahul Nimaya, Raul Nimaiyar, Rahul R
Phone and address:
789 Blue Sage Dr, Sunnyvale, CA 94086
(408) 733-8705
Related to:
Shivani Goel, 51
Connected to:
Cliff Nimako, 72Lauren E Nimal, 43Betty J Niman, 98Georgianna M Niman, 77Rose M Niman, 78Zachary P Niman, 27Claudia S Nimar, 66Stacy L Nimas, 52Dean M Nimax, 66Carlo Nimb, 46

Rahul Nimaiyar Phones & Addresses

  • 789 Blue Sage Dr, Sunnyvale, CA 94086 (408) 733-8705 (408) 774-1672
  • Santa Clara, CA
  • Cupertino, CA
  • Milpitas, CA

Work

Company: Xilinx 2017 Position: Director, machine learning

Education

Degree: Master of Business Administration, Masters School / High School: Northwestern University - Kellogg School of Management 2010 to 2012 Specialities: Marketing, Finance

Skills

Integrated Circuit Design • Start Ups • Product Development • Product Management • Strategic Partnerships • Asic • Cross Functional Team Leadership • Semiconductors • Eda • Microprocessors • Ic • Product Planning • Market Analysis • Marketing Strategy • Tcl • Contract Negotiation • Management • Technical Product Management • Cross Functional Relationships • Product Differentiation • Business Strategy • Soc • Program Management • Integrated Circuits

Industries

Semiconductors

Resumes

Resumes

Rahul Nimaiyar Photo 1

Director, Machine Learning

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Location:
Sunnyvale, CA
Industry:
Semiconductors
Work:
Xilinx
Director, Machine Learning
Violin Systems Dec 2015 - Dec 2016
Director, Product Management and Strategy
Stealth Apr 2015 - Nov 2015
Co-Founder and Chief Executive Officer
Achronix Semiconductor Corporation 2013 - Mar 2015
Senior Director, Strategic Business Development and Strategic Planning
Achronix Semiconductor Corporation 2011 - 2013
Vice President, Product Development
Education:
Northwestern University - Kellogg School of Management 2010 - 2012
Master of Business Administration, Masters, Marketing, Finance Stanford University 1999 - 2003
Indian Institute of Technology, Kharagpur 1992 - 1996
Bachelors, Bachelor of Technology, Electrical Engineering San Jose State University
Master of Science, Masters, Electrical Engineering
Skills:
Integrated Circuit Design
Start Ups
Product Development
Product Management
Strategic Partnerships
Asic
Cross Functional Team Leadership
Semiconductors
Eda
Microprocessors
Ic
Product Planning
Market Analysis
Marketing Strategy
Tcl
Contract Negotiation
Management
Technical Product Management
Cross Functional Relationships
Product Differentiation
Business Strategy
Soc
Program Management
Integrated Circuits

Publications

Us Patents

Reset Signal Distribution

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US Patent:
8072250, Dec 6, 2011
Filed:
Sep 14, 2009
Appl. No.:
12/559009
Inventors:
Ravi Kurlagunda - Fremont CA, US
Ravi Sunkavalli - Milpitas CA, US
Vijay Bantval - Cherry Hill NJ, US
Rahul Nimaiyar - Sunnyvale CA, US
Assignee:
Achronix Semiconductor Corporation - Santa Clara CA
International Classification:
H03K 3/02
US Classification:
327198, 327142, 327291, 327293, 326 93
Abstract:
Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. On or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.

Source-Synchronous Clocking

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US Patent:
8228101, Jul 24, 2012
Filed:
Sep 14, 2009
Appl. No.:
12/558985
Inventors:
Rahul Nimaiyar - Sunnyvale CA, US
Ravi Sunkavalli - Milpitas CA, US
Assignee:
Achronix Semiconductor Corporation - Santa Clara CA
International Classification:
H03L 7/00
US Classification:
327152, 327144, 327149, 327153
Abstract:
Methods, circuits and systems for balanced distribution of source-synchronous clock signals are described. Multiple data sets together with one or more clock signals associated with the multiple data sets may be received at a number of interface devices. The multiple data sets may be captured in a number of data buffers. The clock signals may be programmably distributed to a group of the multiple data buffers that retain the one or more data sets, using a balanced clock network. Additional methods, circuits, and systems are disclosed.

Reset Signal Distribution

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US Patent:
8305124, Nov 6, 2012
Filed:
Dec 2, 2011
Appl. No.:
13/310382
Inventors:
Ravi Kurlagunda - Fremont CA, US
Ravi Sunkavalli - Milpitas CA, US
Vijay Bantval - Cherry Hill NJ, US
Rahul Nimaiyar - Sunnyvale CA, US
Assignee:
Achronix Semiconductor Corporation - Santa Clara CA
International Classification:
H03K 3/02
US Classification:
327198, 327142, 327291, 327293, 326 93
Abstract:
Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. One or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.

Hierarchical Global Clock Tree

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US Patent:
8638138, Jan 28, 2014
Filed:
Sep 14, 2009
Appl. No.:
12/559040
Inventors:
Ravi Sunkavalli - Milpitas CA, US
Rahul Nimaiyar - Sunnyvale CA, US
Ravi Kurlagunda - Fremont CA, US
Vijay Bantval - Cherry Hill NJ, US
Assignee:
Achronix Semiconductor Corporation - Santa Clara CA
International Classification:
H03L 7/06
US Classification:
327156, 327147
Abstract:
Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.

Voltage Tolerant Input/Output Circuit

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US Patent:
6369619, Apr 9, 2002
Filed:
Jul 14, 2000
Appl. No.:
09/615959
Inventors:
Jamil Kawa - Santa Clara CA
Rahul Nimaiyar - Cupertino CA
Puneet Sawhney - San Jose CA
Anwar Awad - Sunnyvale CA
Assignee:
Artisan Components, Inc. - Sunnyvale CA
International Classification:
G05F 110
US Classification:
327108, 327535
Abstract:
The present invention provides a voltage tolerant input/output circuit configured to ensure proper interface tolerance between various close voltages in deep sub-micron circuits without any DC leakage. The voltage tolerant input/output circuit includes (1) an arbiter circuit logically configured to ensure that a gate of a P-driver of the voltage tolerant input/output circuit is biased at the higher of an input/output voltage and an input/output supply voltage when the P-driver is tri-stated, (2) a bias circuit logically configured to biased a floating N-well of the P-driver to ensure that no parasitic diodes formed between any source or drain of a p-device of the voltage tolerant input/output circuit and the N-well of the P-driver is forward biased, and (3) a driver circuit comprising the P-driver.

Hierarchical Global Clock Tree

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US Patent:
20140201560, Jul 17, 2014
Filed:
Jan 21, 2014
Appl. No.:
14/159869
Inventors:
- Santa Clara CA, US
Rahul Nimaiyar - Sunnyvale CA, US
Ravi Kurlagunda - Fremont CA, US
Vijay Bantval - Cherry Hill NJ, US
Assignee:
Achronix Semiconductor Corporation - Santa Clara CA
International Classification:
G06F 1/06
US Classification:
713502
Abstract:
Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.
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Rahul Nimaiyar from Sunnyvale, CA, age ~50 Get Report