Resumes
Resumes
Raghu Papily
View pageLocation:
Austin, TX
Industry:
Semiconductors
Work:
AMD
Member of Technical Staff
AMD Sep 2011 - Jun 2013
Sr Verification Engineer
Nethra Imaging Inc. Feb 2009 - Sep 2011
DESIGN VERIFICATION ENGINEER
ServerEngines May 2006 - Nov 2008
ASIC Design/Verification Engineer
Member of Technical Staff
AMD Sep 2011 - Jun 2013
Sr Verification Engineer
Nethra Imaging Inc. Feb 2009 - Sep 2011
DESIGN VERIFICATION ENGINEER
ServerEngines May 2006 - Nov 2008
ASIC Design/Verification Engineer
Education:
The University of Texas at El Paso 2005 - 2006
MS, Computer Engineering
MS, Computer Engineering
Skills:
Systemverilog
Open Verification
Open Verification Methodology
Verilog
Functional Verification
Open Verification
Open Verification Methodology
Verilog
Functional Verification
Raghu Papily Santa Clara, CA
View pageWork:
Nethra Imaging Inc
Mar 2009 to 2000
ASIC/FPGA VERIFICATION ENGINEER
Server Engines
Austin, TX
May 2006 to Nov 2008
ASIC DESIGN ENGINEER
University of Texas
El Paso, TX
May 2005 to Jul 2006
RESEARCH ASSISTANT
University of Texas
May 2005 to Jul 2006
Pilot Management ASIC
DIGITAL DESIGN LAB
Aug 2004 to Dec 2005
TEACHING ASSISTANT
Mar 2009 to 2000
ASIC/FPGA VERIFICATION ENGINEER
Server Engines
Austin, TX
May 2006 to Nov 2008
ASIC DESIGN ENGINEER
University of Texas
El Paso, TX
May 2005 to Jul 2006
RESEARCH ASSISTANT
University of Texas
May 2005 to Jul 2006
Pilot Management ASIC
DIGITAL DESIGN LAB
Aug 2004 to Dec 2005
TEACHING ASSISTANT
Education:
University of Texas
El Paso, TX
Jan 2005 to Jul 2006
Master of Science in Computer Engineering
Osmania University
Jun 2000 to May 2004
Bachelor of Engineering in Electrical & Electronics Engg
El Paso, TX
Jan 2005 to Jul 2006
Master of Science in Computer Engineering
Osmania University
Jun 2000 to May 2004
Bachelor of Engineering in Electrical & Electronics Engg