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Rachid Naim Helaihel

from Menlo Park, CA
Age ~54
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Also known as:
Rachid N Helaihel, Rachid H Helaihel, Rashad N Helaihel
Related to:
Rania Helaihel
Connected to:
Albert J Helaire, 80Falicity Helaire, 39Helen A Helaire, 74Terry W Helaire, 52Akram A Helal, 48Alanna J Helal, 38Deanna R Helal, 32Doaa A Helal, 42Jumana R Helal, 48Kathleen M Helal, 54

Rachid Helaihel Phones & Addresses

  • Menlo Park, CA
  • Palo Alto, CA
  • 750 N Shoreline Blvd, Mountain View, CA 94043 (650) 903-4185 (650) 964-2841 (650) 967-2678
  • Waterbury, CT
  • 750 N Shoreline Blvd, Mountain View, CA 94043 (650) 922-4258

Work

Position: Installation, Maintenance, and Repair Occupations

Education

Degree: Associate degree or higher

Resumes

Resumes

Rachid Helaihel Photo 1

Rachid Helaihel

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Location:
San Francisco Bay Area
Industry:
Computer Software
Rachid Helaihel Photo 2

Rachid Helaihel

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Publications

Us Patents

Efficient Exhaustive Path-Based Static Timing Analysis Using A Fast Estimation Technique

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US Patent:
8079004, Dec 13, 2011
Filed:
Apr 30, 2009
Appl. No.:
12/433203
Inventors:
Cristian Soviani - Santa Clara CA, US
Rachid N. Helaihel - Mountain View CA, US
Khalid Rahmat - Fremont CA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716108, 716113, 716136, 703 16
Abstract:
One embodiment of the present invention provides a system that performs an efficient path-based static timing analysis (STA) in a circuit design. During operation, the system identifies a set of paths within the circuit design, wherein each path includes one or more segments. For a path in the set of paths, the system determines if at least one segment in the path is shared with a different path which was previously computed by performing a path-based STA, wherein the at least one segment in the different path is associated with previously computed path-based timing information. If so, the system then performs an estimation of a path-based delay for the path based at least on the path-based timing information associated with the shared segment in the different path. Otherwise, the system computes a path-based delay for the path by performing a path-based STA on the path.

System And Method For Optimizing Exceptions

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US Patent:
20040210861, Oct 21, 2004
Filed:
Apr 16, 2003
Appl. No.:
10/417926
Inventors:
Kayhan Kucukcakar - Sunnyvale CA, US
Rachid Helaihel - Mountain View CA, US
Assignee:
Synopsys, Inc.
International Classification:
G06F017/50
US Classification:
716/006000, 716/005000
Abstract:
A method and system of optimizing exceptions to default timing constraints for use in integrated circuit design tools is described. A list of exceptions is accessed and optimized to generate a new list of exceptions. Optimizations may include: elimination of redundant information, resolution of conflicting information, and other transformations. The new list allows more efficient timing analysis, synthesis, placement, routing, noise analysis, power analysis, reliability analysis, and other operations to be performed by EDA tools.

Reducing Memory Used To Store Totals In Static Timing Analysis

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US Patent:
20120278647, Nov 1, 2012
Filed:
Apr 27, 2011
Appl. No.:
13/095719
Inventors:
Sarvesh Bhardwaj - Fremont CA, US
Khalid Rahmat - Fremont CA, US
Kayhan Kucukcakar - Los Altos CA, US
Rachid Helaihel - Mountain View CA, US
International Classification:
G06F 1/12
US Classification:
713401
Abstract:
A system and a method are disclosed for reducing memory used in storing totals during static timing analysis. Totals are stored at various points along paths analyzed in static timing analysis. Some totals may not be merged for reasons including differing clock re-convergence pessimism removal (CRPR) dominators, exceptions, or clocks. Totals at a point may be stored in a super-tag mapping table and replaced at the point with a super-tag. The super-tag includes a super-tag ID referencing the totals stored in the super-tag mapping table. The super-tag also includes a time delay value. The time delay value allows the super-tag ID to be reused in other super-tags at other points while still storing total time delays at the other points. Therefore, the memory used to store totals is reduced in many situations.
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Rachid Naim Helaihel from Menlo Park, CA, age ~54 Get Report