Qwai Hoong Low

6425179, Jul 30, 2002

Oct 12, 1999

09/417255

Qwai H. Low - Cupertino CA
Chok J. Chia - Cupertino CA
Ramaswamy Ranganathan - Saratoga CA

LSI Logic Corporation - Milpitas CA

M05K 334

29840, 361704, 174 163, 174 524, 29841, 29842, 29846

According to the present invention, a method for creating a package for a semiconductor die, the package comprising a flexible tape, comprises the following steps. A support with an opening has a plurality of arms extending through at a portion of the opening. For example, for a square opening, there may be eight arms, two extending from each side of the opening. The arms preferably form a âzâ shape or some other shape with a transverse component. The flexible tape is then attached to the ends of the arms within the opening such that the flexible tape is supported by the arms. A die is attached to the flexible tape, the die is preferably covered with a molding compound, and the die/flexible tape assembly is scribed from the support, thereby creating an individual package.

6429534, Aug 6, 2002

Jan 6, 2000

09/478972

Qwai H. Low - Cupertino CA
Chok J. Chia - Cupertino CA
Maniam Alagaratnam - Cupertino CA

LSI Logic Corporation - Milpitas CA

H01L 2348

257784, 257700, 257692, 257695, 257672, 257676

Provided is an interposer tape which provides electrical communication between a die and a packaging substrate. The dimensions of the interposer tape may vary to accommodate a variety of die sizes for the same packaging substrate. The interposer tape includes an array of traces. A first set of wire bonds is formed between the array of traces and the die. A second set of wire bonds is formed between the array of traces and the packaging substrate.

6486002, Nov 26, 2002

Jun 27, 2001

09/894718

Qwai H. Low - Cupertino CA
Ramaswamy Ranganathan - Saratoga CA

LSI Logic Corporation - Milpitas CA

H01L 2144

438108, 438107, 438111, 427 96, 427282

An improved tape substrate design for a semiconductor package is disclosed. The tape substrate semiconductor package includes a plurality of die pads, a plurality of vias, and a pattern of metal traces interconnected between the die pads and the vias to form circuitry on the tape substrate. According to the method and apparatus of the present invention an extra metal layer is added at the circuitry to increase rigidity of the tape substrate, thereby reducing warpage without adding to the thickness of the tape substrate package.

6489571, Dec 3, 2002

Oct 31, 2000

09/703199

Chok J. Chia - Cupertino CA
Qwai H. Low - Cupertino CA
Patrick Variot - Los Gatos CA

LSI Logic Corporation - Milpitas CA

H05K 109

174258, 174261, 257737, 257738, 361767, 361768

A molded tape ball grid array package includes a molding compound and a tape substrate having a top surface for mounting a die thereon, a bottom surface for attaching solder balls, and vias for forming connections between the solder balls and the die wherein the molding compound surrounds the die and the tape substrate.

6573113, Jun 3, 2003

Sep 4, 2001

09/946033

Qwai H. Low - Cupertino CA
Ramaswamy Ranganathan - Saratoga CA

LSI Logic Corporation - Milpitas CA

H01L 2166

438 18, 438 14

An integrated circuit topography is provided which includes at least two rows of bonding pads. Each row of bonding pads is attributed a row of probe pads. One row of probe pads is contained within the scribe area and suffices as a sacrificial row of probe pads. The other row of probe pads is placed toward the interior of the integrated circuit. The rows of bonding pads and probe pads extend along parallel axis around all four sides of the integrated circuit. Every other bonding pad within one row of bonding pads is connected to every other probe pad within the scribe area, and every other bonding pad within the other rows of bonding pads is connected to every probe pad within the row of probe pads interior to the integrated circuit. This allows a fan-out configuration of the bonding pads to probe pads for purposes of probing electrical performance of the integrated circuit without having to use selected ones of the bonding pads. This prevents jeopardizing the integrity of the bonding pad by gouging out the bonding pad during probe operation.

6603200, Aug 5, 2003

Sep 12, 1997

08/928826

Qwai H. Low - Cupertino CA
Chok J. Chia - Cupertino CA

LSI Logic Corporation - Milpitas CA

H01L 23053

257700, 257691

An integrated circuit package includes a connector board and plural levels of individual conductors and conductive vias disposed through the connector board to form electrical connections between external connection pads on an undersurface of the connector board and finger connections on the upper surface of the connector board. An integrated circuit die is mounted in a central region of the connector board within confines of the individual conductors that are arranged about the die, and wire bond connections are formed between selected ones of the finger connections, the individual conductors, and the connection pads on the integrated circuit die to provide distributed connections for ground and power at one or more operating voltage levels on the individual conductors.

6743979, Jun 1, 2004

Aug 29, 2003

10/652453

Michael J. Berman - West Linn OR
Aftab Ahmad - Lake Oswego OR
Qwai H. Low - Cupertino CA
Chok J. Chia - Cupertino CA
Ramaswamy Ranganathan - Saratoga CA

LSI Logic Corporation - Milpitas CA

H05K 506

174 522, 257784, 257787

An integrated circuit, including a substrate with circuitry formed therein, where the substrate has a peripheral edge. Also included are a top most electrically conductive layer and an underlying electrically conductive layer. Outer bonding pads are disposed in an outer ring, and are formed within the top most layer. Inner bonding pads are disposed in an inner ring, and are formed within the top most layer. Inner connectors electrically connect the inner bonding pads to the circuitry. The inner connectors are formed within the underlying layer, and have a width that is less than the width of the inner bonding pads, thereby defining a gap between the inner connectors. Outer connectors electrically connect the outer bonding pads to the circuitry. The outer connectors are formed within the underlying layer, and have a width that is less than the width of the gap between the inner connectors.

6781150, Aug 24, 2004

Aug 28, 2002

10/229601

Qwai H. Low - Cupertino CA
Ramaswamy Ranganathan - Saratoga CA
Anwar Ali - San Jose CA
Tauman T. Lau - San Jose CA

LSI Logic Corporation - Milpitas CA

H01L 2358

257 48, 257700, 257758

An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer. The sensing layer immediately underlies the at least one of the non electrically conductive layers in the test structure that has no vias formed therein.