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Qinghua Q Chen

from McKinney, TX
Age ~56
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Also known as:
David Qinghua Chen, David Q Chen, Qing Hua Chen, Oinghua Chen, Quinghua Chen, Hua Peng
Related to:
Jiajun J Lin, 71
Connected to:
Abre G Chen, 65Adele Chen, 52Adeline K Chen, 39Ai M Chen, 60Ai C Chen, 78Aiping Chen, 63Alen Y Chen, 68Alma Chen, 29Amanda Chen, 44Amanda T Chen, 62

Qinghua Chen Phones & Addresses

  • McKinney, TX
  • San Jose, CA
  • 13888 Malcom Ave, Saratoga, CA 95070
  • Tucson, AZ
  • Campbell, CA
  • Mountain View, CA
  • Colton, TX
  • College Station, TX

Resumes

Resumes

Qinghua Chen Photo 1

Qinghua Chen

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Work:
Nia 2007 - 2010
Biologist
Qinghua Chen Photo 2

Qinghua Chen

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Qinghua Chen
Managing
Bestpcb Design LLC
Product Design Engineering Services Engi · Product Design, Engineering Services, En
13888 Malcom Ave, Saratoga, CA 95070
Qinghua Chen
President
INTRINSIC LABORATORIES CORPORATION
Business Services at Non-Commercial Site · Nonclassifiable Establishments
3413 Mira Vis, San Jose, CA 95132
1424 Strauss Way, San Jose, CA 95132

Publications

Us Patents

Programmable Sfp Or Sfp+ Module

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US Patent:
8462838, Jun 11, 2013
Filed:
Dec 4, 2009
Appl. No.:
12/631271
Inventors:
Qinghua Chen - Saratoga CA, US
Maurilio De Nicolo - Saratoga CA, US
Stephen Ong - Fremont CA, US
Richard Brooks - Palo Alto CA, US
Liming Yin - San Jose CA, US
Assignee:
Cisco Technology, Inc. - San Jose CA
International Classification:
H03K 5/159
US Classification:
375229, 375219
Abstract:
Various example embodiments are disclosed. According to one example embodiment, a small form factor pluggable (SFP or SFP+) module may include an equalizer and a logic controller. The equalizer may be configured to receive data, provide signal information to a logic controller based on the received data, equalize the data based on equalization instructions received from the logic controller, and transmit the equalized data. The logic controller may be configured to transmit the signal information received from the equalizer receive programming instructions provide the equalization instructions to the equalizer based on the programming instructions, receive control inputs associated with the data, and provide status outputs based on the control inputs and the programming instructions. The SFP or SFP+ module may be configured to plug into a small form factor (SFF) host connector.

Duty Cycle Optimized Prescaler

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US Patent:
62687514, Jul 31, 2001
Filed:
Dec 3, 1999
Appl. No.:
9/454933
Inventors:
Qinghua Chen - Campbell CA
Khodor Elnashar - Dallas TX
Kishore Mishra - Folsom CA
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03K 3017
H03K 504
H03K 708
US Classification:
327175
Abstract:
A Duty cycle optimized prescaler (10) optimizes the clock duty cycle as close as possible to fifty percent. This is achieved by employing two count by two counters (11,12), one (12)to count negative edges of the clock pulse, and one (11)to count positive edges of the clock pulse. Each counter (11,12) output is connected to a comparator (14,15) which compares each counter output (11,12)to a prescaler setting (13). The comparators (14,15) outputs are input to an OR gate (16), the output of which, when, a logic 1, resets the counters(11,12) and toggles a flip-flop circuit (17) providing a clock output signal.
Control profile
Qinghua Q Chen from McKinney, TX, age ~56 Get Report