Puneet Khanna

20130224944, Aug 29, 2013

Feb 27, 2012

13/405414

Puneet Khanna - Wappingers Falls NY, US
Katherina Babich - Cold Springs NY, US
Catherine Labelle - Wappingers Falls NY, US

GLOBALFOUNDRIES Inc. - Grand Cayman

H01L 21/28

438595, 257E2119

Methods for fabricating integrated circuits using tailored chamfered gate liner profiles are provided. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a dummy gate electrode overlying a semiconductor substrate and forming a liner on sidewalls of the dummy gate electrode. A dielectric material is deposited overlying the dummy gate electrode, the liner, and the substrate. The dummy gate electrode is exposed by chemical mechanical planarization. A portion of the dummy gate electrode is removed and the liner is isotropically etched such that it has a chamfered surface. A remainder of the dummy gate electrode is removed to form an opening that is filled with a metal.

20140070358, Mar 13, 2014

Sep 12, 2012

13/612032

Yi Qi - Fishkill NY, US
Puneet Khanna - Wappingers Falls NY, US
Srikanth Samavedam - Fishkill NY, US
Vara G. Vakada - Beacon NY, US
Michael P. Ganz - Fishkill NY, US
Sri Charan Vemula - Fishkill NY, US
Laegu Kang - Hopewell Junction NY, US
Bharat V. Krishnan - Clifton Park NY, US

GLOBALFOUNDRIES Inc. - Grand Cayman

H01L 29/06
H01L 21/76

257499, 438400, 257E2154, 257E29005

A methodology is disclosed enabling the formation of silicon trench profiles for devices, such as SSRW FETs, having a resultant profile that enables desirable epitaxial growth of semiconductor materials. Embodiments include forming a trench in a silicon wafer between STI regions, thermally treating the silicon surfaces of the trench, and forming Si:C in the trench. The process eliminates a need for an isotropic silicon etch to achieve a desirable flat surface. Further, the flat bottom surface provides a desirable surface for epitaxial growth of semiconductor materials, such as Si:C.

20180047641, Feb 15, 2018

Oct 24, 2017

15/792357

- Grand Cayman, KY
Laegu Kang - Hopewell Junction NY, US
Michael Ganz - Clifton Park NY, US
Yi Qi - Fishkill NY, US
Puneet Khanna - Clifton Park NY, US
Srikanth Balaji Samavedam - Fishkill NY, US
Sri Charan Vemula - Clifton Park NY, US
Manfred Eller - Beacon NY, US

H01L 21/8238
H01L 27/092

A device includes a substrate having an N-active region and a P-active region, a layer of silicon-carbon positioned on an upper surface of the N-active region, a first layer of a first semiconductor material positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on an upper surface of the P-active region, and a layer of a second semiconductor material positioned on the second layer of the first semiconductor material. An N-type transistor is positioned in and above the N-active region and a P-type transistor is positioned in and above the P-active region.

20160035630, Feb 4, 2016

Oct 14, 2015

14/882640

- Grand Cayman, KY
Laegu Kang - Hopewell Junction NY, US
Michael Ganz - Clifton Park NY, US
Yi Qi - Fishkill NY, US
Puneet Khanna - Clifton Park NY, US
Srikanth Balaji Samavedam - Fishkill NY, US
Sri Charan Vemula - Clifton Park NY, US
Manfred Eller - Beacon NY, US

H01L 21/8238
H01L 27/092

One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the N-active region while masking the P-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the P-active region while masking the N-active region, forming an N-type transistor in and above the N-active region and forming a P-type transistor in and above the P-active region.

20150249129, Sep 3, 2015

May 19, 2015

14/716045

- Grand Cayman, KY
Vara Govindeswara Reddy VAKADA - Fishkill NY, US
Michael GANZ - Fishkill NY, US
Yi QI - Fishkill NY, US
Puneet KHANNA - Wappingers Falls NY, US
Sri Charan VEMULA - Fishkill NY, US
Srikanth SAMAVEDAM - Fishkill NY, US

H01L 29/06
H01L 29/167
H01L 29/10

A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.

20150129983, May 14, 2015

Nov 14, 2013

14/079757

- Grand Cayman KY, US
Hyucksoo YANG - Watervliet NY, US
Bingwu LIU - Ballston Spa NY, US
Puneet KHANNA - Clifton Park NY, US
Lun ZHAO - Ballston Lake NY, US

Globalfoundries Inc. - Grand Cayman KY

H01L 29/78
H01L 29/08
H01L 29/66

257401, 438283

Fin-type transistor fabrication methods and structures are provided having extended embedded stress elements. The methods include, for example: providing a gate structure extending over a fin extending above a substrate; using isotropic etching and anisotropic etching to form an extended cavity within the fin, where the extended cavity in part undercuts the gate structure, and where the using of the isotropic etching and the anisotropic etching deepens the extended cavity into the fin below the undercut gate structure; and forming an embedded stress element at least partially within the extended cavity, including below the gate structure.

20150087134, Mar 26, 2015

Sep 20, 2013

14/032978

- Grand Cayman, KY
Hsin-Neng TAI - Clifton Park NY, US
Puneet KHANNA - Clifton Park NY, US
Zhenyu HU - Clifton Park NY, US
Huey-Ming WANG - Ballston Lake NY, US

GLOBALFOUNDRIES Inc. - Grand Cayman

H01L 21/762

438424

Methods of facilitating isolation region uniformity include: patterning a semiconductor substrate to form at least one isolation opening within the semiconductor substrate, the patterning comprising leaving, at least in part, a protective hard mask above a portion of the semiconductor substrate; providing an insulating material within and over the at least one isolation opening, and planarizing the insulating material to facilitate fabricating an isolation region within the semiconductor substrate; stopping the planarizing on the protective hard mask and exposing at least a portion of the protective hard mask above the portion of the semiconductor substrate; and non-selectively removing a remaining portion of the insulating material over the at least one isolation opening and the exposed protective hard mask above the portion of the semiconductor substrate while leaving the insulating material within the at least one isolation opening and exposing upper surfaces of the semiconductor substrate, to facilitate isolation region uniformity.

20140367751, Dec 18, 2014

Jun 14, 2013

13/918622

- Grand Cayman, KY
Hyucksoo YANG - Watervliet NY, US
Puneet KHANNA - Clifton Park NY, US

H01L 21/28
H01L 21/306
H01L 29/78

257288, 438585

A method for etching FinFET spacers by inserting a Si recess step directly after the traditional spacer ME step and the resulting device are provided. Embodiments include forming a gate on a substrate having a silicon fin, the gate having a nitride cap on an upper surface thereof and an oxide cap on an upper surface of the nitride cap; forming a dielectric layer over the silicon fin and the gate; removing the dielectric layer from an upper surface of the oxide cap and an upper surface of the silicon fin; recessing the silicon fin; and removing the dielectric layer from side surfaces of the silicon fin and the remaining silicon fin.