Resumes
Resumes
Front End Silicon Circuit Design Engineer At Intel Labs (Bangalore Design Lab)
View pagePosition:
Front End Silicon Circuit Design Engineer at Intel India Technology Pvt Ltd
Location:
Bengaluru, Karnataka, India
Industry:
Computer Hardware
Work:
Intel India Technology Pvt Ltd since May 2011
Front End Silicon Circuit Design Engineer
Intel, Folsom, CA Feb 2008 - Apr 2011
Component Design Engineer in the Intel Architecture Group (IAG)
Syracuse University, NY Jun 2003 - Dec 2007
Graduate Research Fellow in the VLSI Systems Design and CAD (VSDCAD) Laboratory
Syracuse University, NY Aug 2004 - May 2007
Teaching Assistant in the Department of Electrical Engineering and Computer Science
Cadence Design Systems, Chelmsford, MA Nov 2001 - Feb 2003
Senior Member of Technical Staff in the Systems and Functional Verification (SFV) Group
Front End Silicon Circuit Design Engineer
Intel, Folsom, CA Feb 2008 - Apr 2011
Component Design Engineer in the Intel Architecture Group (IAG)
Syracuse University, NY Jun 2003 - Dec 2007
Graduate Research Fellow in the VLSI Systems Design and CAD (VSDCAD) Laboratory
Syracuse University, NY Aug 2004 - May 2007
Teaching Assistant in the Department of Electrical Engineering and Computer Science
Cadence Design Systems, Chelmsford, MA Nov 2001 - Feb 2003
Senior Member of Technical Staff in the Systems and Functional Verification (SFV) Group
Education:
Syracuse University 2003 - 2007
Ph.D, Computer Engineering University of Cincinnati 1996 - 1999
M.S, Computer Engineering University of Madras 1992 - 1996
B.E, Computer Science and Engineering St. John's English School and Junior College, Besant Nagar, Madras 1990 - 1992
CBSE - 12th Std, Maths, Physics, Chemistry and Computer Science
Ph.D, Computer Engineering University of Cincinnati 1996 - 1999
M.S, Computer Engineering University of Madras 1992 - 1996
B.E, Computer Science and Engineering St. John's English School and Junior College, Besant Nagar, Madras 1990 - 1992
CBSE - 12th Std, Maths, Physics, Chemistry and Computer Science
Skills:
EDA
R&D
Verilog
VLSI
ASIC
SoC
VHDL
SystemVerilog
ModelSim
Computer Architecture
RTL design
Functional Verification
Integrated Circuit Design
Algorithms
FPGA
Logic Design
Low-power Design
R&D
Verilog
VLSI
ASIC
SoC
VHDL
SystemVerilog
ModelSim
Computer Architecture
RTL design
Functional Verification
Integrated Circuit Design
Algorithms
FPGA
Logic Design
Low-power Design
Interests:
VLSI, Low-Power Design, Simulation/Emulation, Validation Tools, EDA
Honor & Awards:
- Intel Division Team Award (August 2010)
- Marquis Who's Who in America, 2010
- Intel Division Team Award (December 2009)
- University Graduate Fellowship, Syracuse University (2003-2007)
- Inducted into the PHI BETA DELTA (φβΔ) Academic Honor Society for International Scholars (February 2004)
- Applause Award, Cadence Design Systems (March 2001)
- Co-Recipient of the Prof. Arun Kumar Choudhury Best Paper Award, 13th IEEE International Conference on VLSI Design, Calcutta, India (January 2000)
- University Graduate Scholarship, University of Cincinnati (1996-1999)
Languages:
English, Hindi, French, Tamil