Resumes
Resumes
Prateek Dujari Phones & Addresses
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1511 Park St, Portland, OR 97201 (503) 228-9826
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731 34Th Ave, Portland, OR 97214 (503) 228-9826
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8808 38Th Ave, College Park, MD 20740
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Seattle, WA
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Johnson City, NY
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Binghamton, NY
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731 SE 34Th Ave, Portland, OR 97214
Work
Position:
Professional/Technical
Education
Degree:
Graduate or professional degree
Publications
Us Patents
Circuit Card Assembly Having Controlled Expansion Properties
View pageUS Patent:
6359372, Mar 19, 2002
Filed:
May 3, 2000
Appl. No.:
09/564144
Inventors:
Prateek Dujari - Portland OR
Terrance J. Dishongh - Hillsboro OR
Bin Lian - Hillsboro OR
Damion T. Searls - Portland OR
Terrance J. Dishongh - Hillsboro OR
Bin Lian - Hillsboro OR
Damion T. Searls - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 4108
US Classification:
310328, 310317
Abstract:
Piezoelectric material is embedded in epoxy layers of circuit cards to control thermal expansion and contraction as a function of temperature changes. A temperature sensor and thermostat generates a controlled voltage as a function of temperature and applies the voltage to piezoelectric blocks within the circuit card. Local areas of the circuit card can have different amounts of piezoelectric material or different thermostats. Piezoelectric blocks can be arranged in regular patterns or can be randomly or pseudo-randomly placed.
Circuit Card Assembly Having Controlled Vibrational Properties
View pageUS Patent:
6486589, Nov 26, 2002
Filed:
May 3, 2000
Appl. No.:
09/563378
Inventors:
Prateek Dujari - Portland OR
Terrance J. Dishongh - Hillsboro OR
Bin Lian - Hillsboro OR
Damion T. Searls - Portland OR
Terrance J. Dishongh - Hillsboro OR
Bin Lian - Hillsboro OR
Damion T. Searls - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
B06B 106
US Classification:
310331, 310328, 310330, 310339
Abstract:
Piezoelectric wafers are affixed to a circuit card to control displacement of the circuit card when vibrated. A trigger wafer located at an anti-node of the dominant mode shape produces a voltage as a function of modal displacement. A control system responsive to the trigger wafer produces voltages that are applied to flex wafers at a different anti-node of the dominant mode shape. The flex wafers expand and contract in a manner that reduces the modal displacement of the circuit card. Multiple flex wafers can exist, affixed to the circuit card substantially opposite each other, or a single flex wafer can exist with a single trigger wafer. The trigger wafer can be located substantially opposite the flex wafer or can be located elsewhere on the circuit card.
Process For Local On-Chip Cooling Of Semiconductor Devices Using Buried Microchannels
View pageUS Patent:
6521516, Feb 18, 2003
Filed:
Jun 29, 2001
Appl. No.:
09/895136
Inventors:
Franklin G. Monzon - Arcadia CA
Prateek Dujari - Portland OR
Bin Lian - Portland OR
Prateek Dujari - Portland OR
Bin Lian - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21425
US Classification:
438514, 257714
Abstract:
A method and apparatus comprising using buried microchannels to cool specific areas of a substrate over which high heat generating elements of integrated circuits, circuits or devices are processed is disclosed. In one embodiment of the method and apparatus comprise running a cooling fluid thorough a buried microchannel under a heat generating element to locally cool the substrate.
Vapor Chamber Active Heat Sink
View pageUS Patent:
6550531, Apr 22, 2003
Filed:
May 16, 2000
Appl. No.:
09/572926
Inventors:
Damion T. Searls - Portland OR
Terrance J. Dishongh - Hillsboro OR
Prateek J. Dujari - Portland OR
Bin Lian - Hillsboro OR
Terrance J. Dishongh - Hillsboro OR
Prateek J. Dujari - Portland OR
Bin Lian - Hillsboro OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
F28D 1500
US Classification:
16510433, 16510426, 361700, 257716
Abstract:
A heat dissipation device including a base portion having a plurality of projections extending therefrom. The base portion may have a vapor chamber defined therein and may have first surface sloped from a central apex portion to edges of the base portion. The vapor chamber includes at least one extension on a vapor chamber upper surface which is adapted to direct a condensed working fluid toward a desired location on a vapor chamber lower surface. The vapor chamber lower surface may have at least one depression to collect a greater portion of the working fluid in a desired location(s).
Electrical Energy-Generating Heat Sink System And Method Of Using Same To Recharge An Energy Storage Device
View pageUS Patent:
6574963, Jun 10, 2003
Filed:
Nov 16, 2001
Appl. No.:
09/991110
Inventors:
Pooya Tadayon - Hillsboro OR
Franklin G. Monzon - Temple City CA
Prateek Dujari - Portland OR
Franklin G. Monzon - Temple City CA
Prateek Dujari - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
F01K 2508
US Classification:
60651, 60671
Abstract:
An electrical energy-generating heat sink system is described herein that provides a convenient and economical method for continuously recharging an energy storage device in electronic devices.
Apparatus And Method To Read Output Information From A Backside Of A Silicon Device
View pageUS Patent:
6624643, Sep 23, 2003
Filed:
Dec 8, 2000
Appl. No.:
09/733461
Inventors:
Terrence J. Dishongh - Hillsboro OR
Prateek Dujari - Portland OR
Bin C. Lian - Portland OR
Damion T. Searls - Portland OR
Prateek Dujari - Portland OR
Bin C. Lian - Portland OR
Damion T. Searls - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G01R 31302
US Classification:
324752, 324750, 324755
Abstract:
Photon emissions from a backside of a silicon device or integrated circuit are detected. The photon emissions can be used for a technique to read output information from the silicon device, as the photon emissions from part of an output signal path for the silicon device. The emitted photons pass through openings of a mask positioned over the backside of the silicon device, and are detected by a photodetector array. Electrical signals are generated from the detected photons, and can be converted to optical signals for subsequent transmission from optical transmitters coupled to the photodetector.
Chip Package Enabling Increased Input/Output Density
View pageUS Patent:
6627978, Sep 30, 2003
Filed:
Sep 28, 2001
Appl. No.:
09/967748
Inventors:
Prateek Dujari - Portland OR
Franklin Monzon - Temple City CA
Pooya Tadayon - Hillsboro OR
Franklin Monzon - Temple City CA
Pooya Tadayon - Hillsboro OR
Assignee:
Intel Corporation - Hillsboro OR
International Classification:
H01L 23495
US Classification:
257667, 257672, 257675, 257706
Abstract:
A device and method for increasing input/output from a die by making electrically conductive microvias connecting the integrated circuit with a backside of the die. The backside electrically conductive microvias connect an integrated circuit in the die to pads on the backside of the die. A superstrate is situated on top of the die and connects to the microvias using controlled collapse chip connections (C4) with a thermal interface material (TIM) surrounding the electrical connections. A superstrate lead system electrically connects the backside pads to wirebonds that connect with either the substrate or directly to the motherboard. Heat dissipates from the die via the TIM to the superstrate to a heat sink situated on top of the superstate.
Semiconductor Device With Components Embedded In Backside Diamond Layer
View pageUS Patent:
6649937, Nov 18, 2003
Filed:
Mar 26, 2002
Appl. No.:
10/109143
Inventors:
Damion T. Searls - Portland OR
Prateek J. Dujari - Portland OR
Bin Lian - Hillsboro OR
Prateek J. Dujari - Portland OR
Bin Lian - Hillsboro OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 310312
US Classification:
257 77, 257712, 257713, 257706, 257707, 257708, 257924
Abstract:
A semiconductor substrate with integrated circuit devices on its front side and a high thermal conductivity layer such as diamond on its back side, with components such as capacitors embedded in the high thermal conductivity layer and coupled to the front side integrated circuits with vias through the substrate.