Resumes
Resumes
Verification Engineer
View pageLocation:
862 Gaspar Vis, San Jose, CA 95126
Industry:
Computer Software
Work:
Microsoft
Verification Engineer
Emulex Dec 2012 - 2015
Engineer Senior
Emulex Dec 2011 - Dec 2012
Engineer
Emulex Mar 2011 - Dec 2011
Engineering Intern
Cisco Jul 2008 - Sep 2009
Hardware Engineer
Verification Engineer
Emulex Dec 2012 - 2015
Engineer Senior
Emulex Dec 2011 - Dec 2012
Engineer
Emulex Mar 2011 - Dec 2011
Engineering Intern
Cisco Jul 2008 - Sep 2009
Hardware Engineer
Education:
San Jose State University 2012 - 2016
Master of Science, Masters, Electrical Engineering San Jose State University 2010 - 2011
Santa Clara University 2009 - 2009
Purdue University 2004 - 2008
Bachelors, Bachelor of Science, Electrical Engineering Brebeuf Jesuit Preparatory School
Master of Science, Masters, Electrical Engineering San Jose State University 2010 - 2011
Santa Clara University 2009 - 2009
Purdue University 2004 - 2008
Bachelors, Bachelor of Science, Electrical Engineering Brebeuf Jesuit Preparatory School
Skills:
Verilog
Asic
Perl
C
Eda
Cadence
Tcl
Soc
Rtl Design
Fpga
Pcie
System Verilog
Logic Design
Vhdl
Physical Design
Systemverilog
Application Specific Integrated Circuits
Functional Verification
Tapeout
Unix Shell Scripting
Implementation
Java
Very Large Scale Integration
Python
Asic
Perl
C
Eda
Cadence
Tcl
Soc
Rtl Design
Fpga
Pcie
System Verilog
Logic Design
Vhdl
Physical Design
Systemverilog
Application Specific Integrated Circuits
Functional Verification
Tapeout
Unix Shell Scripting
Implementation
Java
Very Large Scale Integration
Python
Languages:
English
Hindi
Spanish
Hindi
Spanish