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Prakash Pati Phones & Addresses

  • Allen, TX
  • 1265 Capitol Ave, San Jose, CA 95132 (408) 254-1169
  • Sunnyvale, CA
  • Dublin, OH
  • Danville, CA
  • Santa Clara, CA
  • 1265 N Capitol Ave APT 158, San Jose, CA 95132 (408) 254-1169

Work

Company: Micro focus Jan 2010 Position: Software architect

Education

Degree: Bachelor of Engineering, Bachelors School / High School: Utkal University 1988 to 1992 Specialities: Computer Science, Engineering

Skills

C# • Agile Methodologies • C++ • Web Applications • .Net • Software Design • Software Development • Microsoft Sql Server • Design Patterns • Sql • Sdlc • Win32 Api • Databases • Asp.net • Software Engineering • Soa • Ajax • Mfc • Objective C • Oracle • Ios Development • Object Oriented Design • Xcode • Cocoa • Iphone Development • Visual Studio • C • Visual C++ • Win32 • Com • Sql Server • Asp • Ooad • Computer Science • Restful Webservices • Soap • Asp.net Mvc • Wcf Services • Entity Framework • Linq • Xml • Json • Oauth • Odbc • Oci • Ado.net • Atl Com • Solid Principles • Test Driven Development • Angularjs • Cloud Computing • Enterprise Software

Languages

English • Hindi • Oriya

Ranks

Certificate: Machine Learning

Industries

Computer Software

Resumes

Resumes

Prakash Pati Photo 1

Software Architect

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Location:
San Francisco, CA
Industry:
Computer Software
Work:
Micro Focus
Software Architect

Binary Element Feb 2008 - Jan 2010
Founder and Chief Architect

Realization Technologies Jan 2003 - Jan 2008
Software Architect

Nortel Oct 1999 - Jan 2003
Staff Software Engineer

Thru-Put Technologies Jul 1997 - Oct 1999
Senior Software Engineer
Education:
Utkal University 1988 - 1992
Bachelor of Engineering, Bachelors, Computer Science, Engineering
Skills:
C#
Agile Methodologies
C++
Web Applications
.Net
Software Design
Software Development
Microsoft Sql Server
Design Patterns
Sql
Sdlc
Win32 Api
Databases
Asp.net
Software Engineering
Soa
Ajax
Mfc
Objective C
Oracle
Ios Development
Object Oriented Design
Xcode
Cocoa
Iphone Development
Visual Studio
C
Visual C++
Win32
Com
Sql Server
Asp
Ooad
Computer Science
Restful Webservices
Soap
Asp.net Mvc
Wcf Services
Entity Framework
Linq
Xml
Json
Oauth
Odbc
Oci
Ado.net
Atl Com
Solid Principles
Test Driven Development
Angularjs
Cloud Computing
Enterprise Software
Languages:
English
Hindi
Oriya
Certifications:
Machine Learning

Business Records

Name / Title
Company / Classification
Phones & Addresses
Prakash Kumar Pati
President
Binary Element Inc.
Computer Software · Mfg Industrial Inorganic Chemicals
1794 Seille Way, San Jose, CA 95131
1794 Seville Way, San Jose, CA 95131
6071 Loma Prieta Dr, San Jose, CA 95123

Publications

Us Patents

Facilitation Of Multi-Project Management Using Task Hierarchy

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US Patent:
7774742, Aug 10, 2010
Filed:
Jun 8, 2005
Appl. No.:
11/147479
Inventors:
Sanjeev Gupta - San Jose CA, US
Ajai Kapoor - San Jose CA, US
Ravi Shankar - San Jose CA, US
Prakash Pati - San Jose CA, US
Subramanian Muthu - Santa Clara CA, US
Anthony Hoang - Milpitas CA, US
Sridharan Chandrasekaran - San Jose CA, US
Assignee:
Realization Technologies, Inc. - San Jose CA
International Classification:
G06F 9/44
US Classification:
717101, 717102, 717103, 717100
Abstract:
A method on a computer for providing critical chain-based project management is disclosed. The method includes receiving at least one project plan for a project comprising a plurality of tasks and calculating a task priority for each of the plurality of tasks based on the at least one project plan. The method further includes receiving at least one sub-task for a first task of the plurality of tasks and assigning the at least one sub-task a task priority identical to the task priority of the first task. In one alternative, the method further includes receiving a new task priority for the first task, assigning the new task priority to the first task and assigning the new task priority to the at least one sub-task of the first task. The method may also include an interface to allow starting of sub-tasks only when the parent task is started.

Facilitation Of Multi-Project Management Using Critical Chain Methodology

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US Patent:
20050097505, May 5, 2005
Filed:
Nov 4, 2003
Appl. No.:
10/700431
Inventors:
Sanjeev Gupta - San Jose CA, US
Ravi Shankar - Sunnyvale CA, US
Ajai Kapoor - Cupertino CA, US
Prakash Pati - San Jose CA, US
Corvin Bazgan - San Carlos CA, US
Subbarao Nimmakayala - Livermore CA, US
Assignee:
Realization Technologies, Inc. - San Jose CA
International Classification:
G06F009/44
US Classification:
717101000
Abstract:
A method on a computer for providing critical chain-based project management across a plurality of projects is disclosed. The method includes generating a plurality of plans, each of the plurality of plans corresponding to one of the plurality of projects, wherein a project comprises at least one task. The method further includes generating buffers for each of the plurality of projects and reconciling project resources among the plurality of projects. The method further includes executing the plurality of project plans, including allowing a user to manage the buffers across the plurality of projects. The user is further provided with information associated with buffers for the plurality of projects, so as to evaluate the status of the plurality of projects. Additionally, the user is provided with task prioritization for any task of the plurality of projects, wherein task prioritization is calculated across the plurality of projects.

Post Facto Identification And Prioritization Of Causes Of Buffer Consumption

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US Patent:
20110106713, May 5, 2011
Filed:
Oct 30, 2009
Appl. No.:
12/610209
Inventors:
Ajai Kapoor - San Jose CA, US
Ravi Shankar - San Jose CA, US
Xiangting Yuan - Pleasanton CA, US
Anthony H. Hoang - Milpitas CA, US
Prakash K. Pati - San Jose CA, US
Assignee:
Realization Technologies, Inc. - San Jose CA
International Classification:
G06Q 10/00
US Classification:
705301
Abstract:
Some embodiments provide a system for determining an aggregate delay associated with a task attribute value. During operation, the system can receive a set of projects, which include completed projects and currently executing projects. Next, the system can determine buffer consumption amounts associated with task chains in each project. A task chain can be a sequence of tasks in the project's task dependency network which ends in the project buffer. The buffer consumption amount associated with a task chain can be the amount of the project buffer that would have been consumed if the tasks in the task chain were the only tasks in the project. Next, the system can select a set of task chains based at least on the buffer consumption amounts. The system can then aggregate task delays for tasks in the set of task chains that are associated with the task attribute value.

Post Facto Identification And Prioritization Of Causes Of Buffer Consumption

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US Patent:
20110107333, May 5, 2011
Filed:
Oct 30, 2009
Appl. No.:
12/610228
Inventors:
Ajai Kapoor - San Jose CA, US
Ravi Shankar - San Jose CA, US
Xiangting Yuan - Pleasanton CA, US
Anthony H. Hoang - Milpitas CA, US
Prakash K. Pati - San Jose CA, US
Assignee:
Realization Technologies, Inc. - San Jose CA
International Classification:
G06F 9/46
US Classification:
718100, 715772
Abstract:
Some embodiments of the present invention provide systems and techniques for collecting task status information. During operation, the system can receive a status update for a task from a task manager through a GUI. Next, the system can determine whether the first status update for the task indicates that the task is delayed. If the status update indicates that the task is delayed, the system can request the task manager to indicate the help needed to resolve the task delay. Next, the system can receive a help needed descriptor from the task manager. Subsequently, the system can receive another status update for the task from the task manager, wherein the status update indicates that the help specified in the help needed descriptor is no longer required. Next, the system can determine an amount of delay associated with the help needed descriptor.

Post Facto Identification And Prioritization Of Causes Of Buffer Consumption

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US Patent:
20110107334, May 5, 2011
Filed:
Oct 30, 2009
Appl. No.:
12/610264
Inventors:
Ajai Kapoor - San Jose CA, US
Ravi Shankar - San Jose CA, US
Xiangting Yuan - Pleasanton CA, US
Anthony H. Hoang - Milpitas CA, US
Prakash K. Pati - San Jose CA, US
Assignee:
REALIZATION TECHNOLOGIES, INC. - San Jose CA
International Classification:
G06F 9/46
US Classification:
718100, 715772
Abstract:
Some embodiments of the present invention provide systems and techniques for determining a start delay and an execution delay for a task. During operation, the system can receive a status update for the task which indicates that the task has started execution. Next, the system can receive a second status update for the task which indicates that the task has completed execution. The system can then determine the start delay for the task by: determining an actual start time using the first status update; and determining a difference between the actual start time and the task's suggested start time. Next, the system can determine the execution delay for the task by: determining an actual execution duration using the first status update and the second status update; and determining a difference between the actual execution duration and the task's planned execution duration.

Facilitation Of Multi-Project Management Using Critical Chain Methodology

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US Patent:
20130096971, Apr 18, 2013
Filed:
Feb 22, 2010
Appl. No.:
12/710335
Inventors:
Sanjeev Gupta - San Jose CA, US
Ravi Shankar - Sunnyvale CA, US
Ajai Kapoor - Cupertino CA, US
Prakash Kumar Pati - San Jose CA, US
Corvin Bazgan - San Carlos CA, US
Subbarao Nimmakayala - Livermore CA, US
International Classification:
G06Q 10/06
US Classification:
705 715
Abstract:
A method on a computer for providing critical chain-based project management across a plurality of projects is disclosed. The method includes generating a plurality of plans, each of the plurality of plans corresponding to one of the plurality of projects, wherein a project comprises at least one task. The method further includes generating buffers for each of the plurality of projects and reconciling project resources among the plurality of projects. The method further includes executing the plurality of project plans, including allowing a user to manage the buffers across the plurality of projects. The user is further provided with information associated with buffers for the plurality of projects, so as to evaluate the status of the plurality of projects. Additionally, the user is provided with task prioritization for any task of the plurality of projects, wherein task prioritization is calculated across the plurality of projects.

Cryptographically Secure Scannable Code To Determine The Authenticity Of Physical Items

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US Patent:
20220366429, Nov 17, 2022
Filed:
May 14, 2021
Appl. No.:
17/320796
Inventors:
Prakash Pati - Allen TX, US
Akshaya Mahapatra - San Jose CA, US
International Classification:
G06Q 30/00
H04L 9/32
G06K 7/14
G06Q 30/02
Abstract:
A system for determining authenticity of an item includes a processor and a memory. The memory includes instructions stored thereon, which when executed by the processor cause the system to assign a unique identifier to an item, generate a digital signature of the unique identifier of the item using a private key of a producing organization, generate a scannable code based on the generated digital signature and/or a base 64 encoded form of the generated digital signature, and embed in the item the scannable code and the unique item identifier, a name of the producing organization, and/or a public key server URL.
Prakash K Pati from Allen, TX, age ~54 Get Report