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Pradeep K Bajpai

from Santa Clara, CA
Age ~46
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Also known as:
Pradeep Kumar Bajpai, Pradeep Baspa, Bajpai K Pradeep, Pradeep I
Connected to:
Hemant Bajpai, 40Mukul Bajpai, 60Nirupama Bajpai, 56Rajneesh Bajpai, 51Sharad Bajpai, 55Shreya Bajpai, 27Swamini Bajpai, 44Usha S Bajpai, 55Gouri S Bajpayee, 80Manil Bajracharya, 53

Pradeep Bajpai Phones & Addresses

  • Santa Clara, CA
  • Sunnyvale, CA
  • 370 Elan Village Ln, San Jose, CA 95134 (408) 449-5139
  • Mountain View, CA

Resumes

Resumes

Pradeep Bajpai Photo 1

Senior Member Technical Staff

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Location:
1332 Casa Ct, Santa Clara, CA 95051
Industry:
Semiconductors
Work:
Cypress Semiconductor Corporation
Senior Member Technical Staff
Cypress Semiconductor Corporation
Senior Principal Design Engineer
Cypress Semiconductor Corporation Jul 2011 - Jul 2014
Principal Design Engineer
Ge Mar 2002 - Oct 2002
Asic Design Engineer
Education:
Indian Institute of Science (Iisc) 2000 - 2001
Masters, Master of Technology Shri G S Institute of Technology & Science 1995 - 1999
Bachelor of Engineering, Bachelors, Electronics, Engineering, Communications Shri Govindram Seksaria Institute of Technology & Science, 23,Park Road, Indore
Indian Institute of Science
Skills:
Application Specific Integrated Circuits
System on A Chip
Low Power Design
Field Programmable Gate Arrays
Systemverilog
Mixed Signal
Functional Verification
Verilog
Usb
Semiconductors
Formal Verification
Silicon Validation
Low Power Verification
Pradeep Bajpai Photo 2

Pradeep Bajpai

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Publications

Us Patents

Circuit And Method For Increasing Universal Serial Bus (Usb) Device Endpoints

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US Patent:
8131890, Mar 6, 2012
Filed:
Mar 24, 2008
Appl. No.:
12/054315
Inventors:
Pradeep Kumar Bajpai - San Jose CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G06F 13/00
G06F 3/00
US Classification:
710 31, 710 30, 710 52, 709236, 711118
Abstract:
A USB control circuit for increasing USB endpoints includes a token detection circuit. The USB control circuit is configured to receive a first logical endpoint (LEP) address and a USB token. The token detection circuit is configured to determine a direction of a USB data transfer in accordance with a USB token type. The USB control circuit includes an endpoint configuration and status control logic circuit in communication with the token detection circuit. The endpoint configuration and status control logic circuit is configured to control configuration and status information associated with each of a plurality of LEP input buffers and LEP output buffers. The USB control circuit is configured to generate a second LEP address in accordance with a combination of the first LEP address and the determined direction to increase a quantity of LEPs without increasing a quantity of physical endpoint buffers of a USB device.

Busy Detection Logic For Asynchronous Communication Port

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US Patent:
8145809, Mar 27, 2012
Filed:
Mar 7, 2008
Appl. No.:
12/044831
Inventors:
Syed Babar Raza - San Jose CA, US
Pradeep Bajpai - San Jose CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G06F 3/00
G06F 1/12
US Classification:
710 58, 710 36, 710 52, 713400
Abstract:
An embodiment of the present invention is directed to a system for synchronizing independent time domain information. The synchronization of the device resource access information allows a memory access device to reliably access memory in a time domain independent of a device issuing requests. The system may synchronize device resource information for requests made by a processor to access (e. g. , read/write) locations of a memory device. The present invention synchronizes the device access information without restricting pulse width of a read/write signal or requiring a high speed clock.

Device, Method, And Protocol For Data Transfer Between Host Device And Device Having Storage Interface

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US Patent:
8315269, Nov 20, 2012
Filed:
Sep 28, 2007
Appl. No.:
11/906033
Inventors:
Jagadeesan Rajamanickam - San Jose CA, US
Dinesh Maheshwari - Fremont CA, US
Stephen Henry Kolokowsky - San Diego CA, US
Pradeep Kumar Bajpai - Sunnyvale CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H04L 12/28
H04L 12/56
G06F 15/16
US Classification:
370419, 709230
Abstract:
A system for transferring data files between a host device and a secondary device can include a bridge device forming at least a portion of the secondary device. The bridge device can have a de-multiplex (de-MUX) data path with an input coupled to a host interface (I/F), a first output coupled to a storage I/F and a second output coupled to a processor I/F. A controller circuit can have control inputs coupled to receive configuration commands from the processor I/F and control outputs coupled to control terminals of the de-MUX data path. The controller circuit enables and maintaining a data path between the host I/F and the first output of the de-MUX data path for a predetermined number of data transfers in response to at least a first configuration data input.

Busy Detection Logic For Asynchronous Communication Port

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US Patent:
8370543, Feb 5, 2013
Filed:
Jun 6, 2011
Appl. No.:
13/154348
Inventors:
Syed Babar Raza - San Jose CA, US
Pradeep Bajpai - San Jose CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G06F 3/00
G06F 1/12
G06F 1/00
US Classification:
710 40, 710 8, 710 58, 713400, 713500
Abstract:
An embodiment of the present invention is directed to a system for synchronizing independent time domain information. The synchronization of the device resource access information allows a memory access device to reliably access memory in a time domain independent of a device issuing requests. The system may synchronize device resource information for requests made by a processor to access (e. g. , read/write) locations of a memory device. The present invention synchronizes the device access information without restricting pulse width of a read/write signal or requiring a high speed clock.

Arbitration Method For Programmable Multiple Clock Domain Bi-Directional Interface

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US Patent:
8589632, Nov 19, 2013
Filed:
Mar 7, 2008
Appl. No.:
12/044862
Inventors:
Sumeet Gupta - San Jose CA, US
Hamid Khodabandehlou - Milpitas CA, US
Pradeep Bajpai - San Jose CA, US
Syed Babar Raza - San Jose CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G06F 12/00
US Classification:
711147, 711137, 710 52
Abstract:
An embodiment of the present invention is directed to a system including a memory interface logic unit for receiving memory access requests and corresponding information, a processor coupled to the memory interface logic, a plurality of pre-fetch buffers for handling memory accesses coupled to the memory interface logic unit, an arbiter logic unit for pre-fetching data into the plurality of pre-fetch buffers, a memory device for storing data coupled to the arbiter logic unit and the plurality of pre-fetch buffers, and busy detection logic for informing the arbiter logic unit of the current operation of the processor. The arbiter logic unit facilitates memory access via pre-fetch buffers of the processor and the memory in different or independent clock domains. The arbiter logic further allows random access without introducing additional latency.

Methods And Physical Computer-Readable Storage Media For Intiating Re-Enumeration Of Usb 3.0 Compatible Devices

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US Patent:
20130086282, Apr 4, 2013
Filed:
Sep 29, 2011
Appl. No.:
13/248326
Inventors:
Pradeep Bajpai - San Jose CA, US
Robert Rundell - Bellevue WA, US
Assignee:
CYPRESS SEMICONDUCTOR CORPORATION - San Jose CA
International Classification:
G06F 3/00
US Classification:
710 8
Abstract:
Methods, physical computer-readable media, and devices are provided that allow re-enumeration to be initiated on a USB 3.0-compatible device. The method includes establishing a connection with a host, transmitting an indicator from the device to the host to cause a Link Training and Status State Machine (LTSSM) of the host to move from active state (U0) to one of SS.Inactive and RX.Detect, synchronizing the device with the host, and presenting a new configuration of the device to the host.

Implementation Of Logical Endpoints In Usb Device

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US Patent:
8099534, Jan 17, 2012
Filed:
Dec 13, 2007
Appl. No.:
11/956273
Inventors:
Syed Babar Raza - San Jose CA, US
Sumeet Gupta - San Jose CA, US
Pradeep Bajpai - San Jose CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G06F 3/00
US Classification:
710 62, 710 52
Abstract:
A method includes receiving an endpoint address and corresponding endpoint data, the endpoint address identifying a logical endpoint associated with the endpoint data, storing the endpoint data to at least one of a plurality of memory buffers corresponding to the identified logical endpoint, and transmitting the endpoint data to a destination according to the endpoint address. A peripheral device includes a logical-to-physical memory map to store an endpoint address and corresponding endpoint data received from a first device, the endpoint address to identify at least one data stream capable of transferring the endpoint data to a second device, and a service unit to retrieve the endpoint address and corresponding endpoint data from the logical-to-physical memory map, and to transfer the endpoint data to the second device in the data stream identified by the endpoint address.

Methods To Remove Dribble Introduced And Regenerate Sync Bits Lost Due To Squelch Delays In Usb High Speed Packet Repeating

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US Patent:
20220190960, Jun 16, 2022
Filed:
Dec 11, 2020
Appl. No.:
17/119903
Inventors:
- San Jose CA, US
Pradeep Kumar Bajpai - Sunnyvale CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H04L 1/00
H04L 12/823
H04L 12/26
H04L 29/06
H04L 12/403
Abstract:
Disclosed are techniques for removing dribble bits following the end-of-packet (EOP) of a High-Speed data packet inserted by the transmission envelope detector of a repeater/hub that interconnects electronic devices compliant with Universal Serial Bus (USB) Specification Revision 2.0 or higher. A physical layer logic (PHY) of a first port of the repeater/hub receives a High-Speed data packet to store a recovered bit stream into an elastic buffer. The recovered bit stream may include dribble bits inserted by the PHY after the EOP. The repeater/hub reads the recovered bit stream from the elastic buffer for transmission through the PHY of a second port. The repeater/hub monitors the EOP. When the EOP is detected, the repeater/hub prevents transmission of the dribble bits of the recovered bit stream following the EOP from the second port, eliminating the intended receiver of the High-Speed data packet from the complexity of dealing with dribble bits.
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Pradeep K Bajpai from Santa Clara, CA, age ~46 Get Report