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Pirooz Peyman Hojabri

from San Jose, CA
Age ~64
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Also known as:
Prooz Hojabri, Pirooz Hojabre, I Pirooz
Phone and address:
967 Hampswood Way, San Jose, CA 95120
(408) 997-2319
Related to:
Clayton M Knight, 35Ann L Chou, 50William Knight, 39Amanda Min, 49Wesley ReedRebecca Reed, 54
Connected to:
Menachem Y Hojda, 42Hikmat J Hojeibane, 43Mohamad H Hojeij, 63Kyle E Hojem, 37Hajime Hoji, 73Forouzan Hojjat, 65Anahid Hojjati, 61Mohammad R Hojjati, 54Sepehr Hojjati, 43Daniel M Hojlo, 65

Pirooz Hojabri Phones & Addresses

  • 967 Hampswood Way, San Jose, CA 95120 (408) 997-2319
  • 1212 Eagle Valley Ct, San Jose, CA 95120
  • San Rafael, CA
  • Milpitas, CA
  • San Francisco, CA
  • Campbell, CA
  • Sunnyvale, CA

Business Records

Name / Title
Company / Classification
Phones & Addresses
Pirooz Hojabri
Apptwee Lp
Business Services at Non-Commercial Site · Nonclassifiable Establishments
967 Hampswood Way, San Jose, CA 95120

Publications

Us Patents

Edc Architecture

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US Patent:
7893858, Feb 22, 2011
Filed:
Mar 5, 2009
Appl. No.:
12/398926
Inventors:
Pirooz Hojabri - San Jose CA, US
Jack Lam - San Jose CA, US
Assignee:
NetLogic Microsystems, Inc. - Santa Clara CA
International Classification:
H03M 1/34
US Classification:
341158, 341161
Abstract:
A method and apparatus for performing pipelined capacitive folding and interpolation analog-to-digital conversion. In one embodiment, the apparatus comprises a multistage pipelined analog-to-digital converter having: a distributed sample/hold and preamp, folding and interpolation unit which combines a plurality of preamplified signals using a capacitive folding and capacitive interpolation; and a decoding unit coupled to decode the output signals from the folding and interpolation unit. The distributed sample/hold and preamp drastically improves the input dynamic range and hence increases ADC over all linearity. This technique offers an inherent dynamic offset cancellation in every sample and can be implemented in submicron CMOS, using the core digital supply.

Systems, Circuits, And Methods For Pipelined Folding And Interpolating Adc Architecture

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US Patent:
8063811, Nov 22, 2011
Filed:
Nov 18, 2010
Appl. No.:
12/949615
Inventors:
Pirooz Hojabri - San Jose CA, US
Jack Lam - San Jose CA, US
Assignee:
NetLogic Microsystems, Inc. - Santa Clara CA
International Classification:
H03M 1/34
US Classification:
341158, 341161
Abstract:
A method and apparatus for performing pipelined capacitive folding and interpolation analog-to-digital conversion. In one embodiment, the apparatus comprises a multistage pipelined analog-to-digital converter having: a distributed sample/hold and preamp, folding and interpolation unit which combines a plurality of preamplified signals using a capacitive folding and capacitive interpolation; and a decoding unit coupled to decode the output signals from the folding and interpolation unit. The distributed sample/hold and preamp drastically improves the input dynamic range and hence increases ADC over all linearity. This technique offers an inherent dynamic offset cancellation in every sample and can be implemented in submicron CMOS, using the core digital supply.

Time Interleaved Analog To Digital Converter Mismatch Correction

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US Patent:
20140022101, Jan 23, 2014
Filed:
Nov 21, 2012
Appl. No.:
13/684031
Inventors:
Pirooz HOJABRI - San Jose CA, US
Masood YOUSEFI - Sunnyvale CA, US
Assignee:
TEKTRONIX, INC. - Beaverton OR
International Classification:
H03M 1/50
US Classification:
341118
Abstract:
A machine-implemented method can include receiving a common input signal over M parallel time-interleaved (TI) analog to digital converter (ADC) channels, determining a multiple-input, multiple-output finite impulse response (FIR) filter structure for correcting bandwidth mismatches between the M parallel TIADC channels, and providing a common output signal comprising TI data corresponding to the M parallel TIADC corrected channels.

Compensation Technique For Parasitic Capacitance

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US Patent:
57443858, Apr 28, 1998
Filed:
Mar 21, 1997
Appl. No.:
8/822989
Inventors:
Pirooz Hojabri - San Jose CA
Assignee:
Plato Labs, Inc. - San Jose CA
International Classification:
H01L 2702
US Classification:
438238
Abstract:
Various circuit techniques to implement continuous-time filters with improved performance are disclosed. The present invention uses RMC type integrators that exhibit lower harmonic distortion. In one embodiment, a novel high-gain two-pole operational amplifier is used along with RMC architecture to achieve lower harmonic distortion. In another embodiment, the present invention uses dummy polysilicon resistors to accurately compensate for the distributed parasitics of the polysilicon resistors used in RMC integrator. In yet another embodiment, the present invention provides an on-chip tuner with a differential architecture for better noise immunity.

Dual Output Signal Paths For Signal Source Channels To Optimize For Bandwidth And Amplitude Range

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US Patent:
20200212926, Jul 2, 2020
Filed:
Sep 30, 2019
Appl. No.:
16/588613
Inventors:
- Beaverton OR, US
Pirooz Hojabri - San Jose CA, US
Assignee:
Tektronix, Inc. - Beaverton OR
International Classification:
H03M 1/66
Abstract:
A signal source device includes at least one digital-to-analog converter, at least one connector, a first output path from the at least one digital-to-analog converter to the at least one connector, and a second output path from the at least one digital-to-analog converter to the at least one connector. A method of generating a analog signal includes generating at least one analog signal from at least one digital-to-analog converter, transmitting a first analog signal of the at least one analog signal along a first output path from the at least one digital-to-analog converter to at least one connector, and transmitting a second analog signal of the at least one analog signal along a second output path from the at least one digital-to-analog converter to the at least one connector.

Joint Optimization Of Fir Filters In A Non-Linear Compensator

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US Patent:
20190312571, Oct 10, 2019
Filed:
Apr 9, 2018
Appl. No.:
15/948121
Inventors:
- Beaverton OR, US
Pirooz Hojabri - San Jose CA, US
Tigran Hovakimyan - Yerevan, AM
Norayr Yengibaryan - Yerevan, AM
Assignee:
Tektronix, Inc. - Beaverton OR
International Classification:
H03H 17/02
G01R 35/00
Abstract:
A mechanism is included for jointly determining filter coefficients for Finite Impulse Response (FIR) filters in a Linear, Memory-less Non-linear (LNL), Linear compensator. Calibration signals are applied to a signal converter input in a test and measurement system. Non-linear signal components are determined in signal output from the signal converter. Non-linear filter components are determined at the LNL compensator based on the calibration signals. The non-linear signal components are then compared to the non-linear filter components. The comparison is then resolved to determine filter coefficients for first stage Finite Impulse Response (FIR) filters and second stage FIR filters in the LNL.

Passive Variable Continuous Time Linear Equalizer With Attenuation And Frequency Control

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US Patent:
20190103999, Apr 4, 2019
Filed:
Aug 29, 2018
Appl. No.:
16/116677
Inventors:
- Beaverton OR, US
Kan Tan - Portland OR, US
Pirooz Hojabri - San Jose CA, US
Assignee:
Tektronix, Inc. - Beaverton OR
International Classification:
H04L 25/03
Abstract:
A continuously or step variable passive noise filter for removing noise from a signal received from a DUT added by a test and measurement instrument channel. The noise filter may include, for example, a splitter splits a signal into at least a first split signal and a second split signal. A first path receives the first split signal and includes a variable attenuator and/or a variable delay line which may be set based on the channel response of the DUT which is connected. The variable attenuator and/or the variable delay line may be continuously or stepped variable, as will be discussed in more detail below. A second path is also included to receive the second split signal and a combiner combines a signal from the first path and a signal from the second path into a combined signal.

Variable Passive Network Noise Filter For Noise Reduction

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US Patent:
20180123626, May 3, 2018
Filed:
Sep 29, 2017
Appl. No.:
15/721591
Inventors:
- Beaverton OR, US
Pirooz Hojabri - San Jose CA, US
Assignee:
Tektronix, Inc. - Beaverton OR
International Classification:
H04B 1/10
H04B 1/04
H04B 1/00
Abstract:
Disclosed is a noise filter. The noise filter includes an input port to receive an analog signal. The noise filter further includes a multiplexer coupled to the input port. The multiplexer separates the analog signal into a plurality of frequency bands. The frequency bands include a high frequency band and a low frequency band. The noise filter also includes a low-band variable attenuator coupled to the multiplexer. The low-band variable attenuator adjustably attenuates the low frequency band relative to the high frequency band.
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Pirooz Peyman Hojabri from San Jose, CA, age ~64 Get Report