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Pinkesh J Shah

from Chandler, AZ
Age ~57
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Also known as:
Pina P Shah, Pina D Shah, Tinkesh J Shah, Purvi J Shah, Pinkesh J Shaw, Shah Pinkesh
Related to:
Pavan Shah, 27Jethalal C ShahShirish N Saraiya, 86Kaushali Shah, 52Pina P Shah, 55Jay S Saraiya, 49Veena S Saraiya, 75Veena J Shah, 80Urvi SaraiyaPurvi J Shah, 47Hemila J Shah, 45
Connected to:
Aadil Shah, 29Aalay D Shah, 33Aamer B Shah, 45Aashiv A Shah, 42Aasim Shah, 56Abdul R Shah, 59Abha H Shah, 53Abida Shah, 67Abu M Shah, 59Aftab H Shah, 67

Pinkesh Shah Phones & Addresses

  • Chandler, AZ
  • Maricopa, AZ
  • 66 Julian Dr, Gilbert, AZ 85296 (480) 756-7623 (480) 456-0918
  • Tempe, AZ
  • 4415 Grant Rd, Tucson, AZ 85712 (520) 318-9987
  • Bayonne, NJ
  • Mesa, AZ
  • Poughkeepsie, NY

Business Records

Name / Title
Company / Classification
Phones & Addresses
Pinkesh Shah
BLUE STAR DEVELOPERS, LLC
3520 S Valero St, Chandler, AZ 85249
66 E Julian Dr, Gilbert, AZ 85296
Pinkesh Shah
Principal
PJSOFT, LLC
Business Services at Non-Commercial Site
66 E Julian Dr, Gilbert, AZ 85296

Publications

Us Patents

Adjusting Power Parameters For Frequency Control In Compute Systems

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US Patent:
20230018221, Jan 19, 2023
Filed:
Sep 26, 2022
Appl. No.:
17/953002
Inventors:
Reshma Pattan - Tuam, IE
Pinkesh Shah - Chandler AZ, US
Chris MacNamara - Limerick, IE
Nikhil Gupta - Portland OR, US
International Classification:
G06F 1/3293
G06F 1/3287
Abstract:
An apparatus can include processor cores and control circuitry coupled to the processor cores. The control circuitry can detect at least one of a power characteristic and a frequency characteristic of at least one of the processor cores. The control circuitry can determine that a frequency control opportunity is present on at least one of the processor cores based on at least one of the power characteristic and the frequency characteristic. The control circuitry can adjust a power parameter of at least one of the processor cores responsive to determining that the frequency control opportunity is present.

Efficient Data Transfer Between A Processor Core And An Accelerator

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US Patent:
20150269074, Sep 24, 2015
Filed:
Mar 24, 2014
Appl. No.:
14/222792
Inventors:
Pinkesh Shah - Chandler AZ, US
Herbert Hum - Portland OR, US
Lingdan Zeng - Chandler AZ, US
International Classification:
G06F 12/08
G06F 13/28
G06F 12/12
Abstract:
A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.

Power Gating A Portion Of A Cache Memory

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US Patent:
20140173206, Jun 19, 2014
Filed:
Mar 5, 2013
Appl. No.:
13/785228
Inventors:
Ren Wang - Portland OR, US
Ahmad Samih - Beaverton OR, US
Eric Delano - Fort Collins CO, US
Pinkesh J. Shah - Chandler AZ, US
Zeshan A. Chishti - Hillsboro OR, US
Christian Maciocco - Portland OR, US
Tsung-Yuan Charlie Tai - Portland OR, US
International Classification:
G06F 12/08
US Classification:
711121
Abstract:
In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.

Power Gating A Portion Of A Cache Memory

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US Patent:
20140173207, Jun 19, 2014
Filed:
Dec 14, 2012
Appl. No.:
13/715613
Inventors:
Ren Wang - Portland OR, US
Ahmad Samih - Beaverton OR, US
Eric Delano - Fort Collins CO, US
Pinkesh J. Shah - Chandler AZ, US
Zeshan A. Chishti - Hillsboro OR, US
Christian Maciocco - Portland OR, US
Tsung-Yuan Charlie Tai - Portland OR, US
International Classification:
G06F 12/08
US Classification:
711122
Abstract:
In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed.

Method And Apparatus For Optimizing Power And Latency On A Link

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US Patent:
20140095944, Apr 3, 2014
Filed:
Sep 29, 2012
Appl. No.:
13/631934
Inventors:
James W. Alexander - Hillsboro OR, US
Buck W. Gremel - Olympia WA, US
Pinkesh J. Shah - Gilbert AZ, US
Malay Trivedi - Chandler AZ, US
Mohan K. Nair - Portland OR, US
International Classification:
G06F 1/26
G06F 11/07
US Classification:
714 48, 713300, 714E11024
Abstract:
An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link.
Control profile
Pinkesh J Shah from Chandler, AZ, age ~57 Get Report