Phillip H Jones

6356972, Mar 12, 2002

Jan 19, 2001

09/765773

Kenneth T. Chin - Cypress TX
Clarence K. Coffee - Pembroke Pines FL
Michael J. Collins - Tomball TX
Jerome J. Johnson - Spring TX
Phillip M. Jones - Spring TX
Robert A. Lester - Houston TX
Gary J. Piccirillo - Cypress TX

Compaq Information Technologies Group, LP - Houston TX

G06F 1314

710310

A computer is provided having a bus interface unit coupled between a processor bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the processor bus for controlling the transfer of cycles from the processor to the peripheral bus and memory bus. Those cycles are initially forwarded as a request, whereby the processor controller includes a memory request queue separate from a peripheral request queue. Requests from the memory and peripheral request queues can be de-queued concurrently to the memory and peripheral buses. This enhances throughput of read and write requests; however, proper ordering of data returned as a result of read requests and data transferred as a result of write requests must be ensured. An in-order queue is also present in the processor controller which records the order in which the requests are dispatched to the peripheral and memory buses from the peripheral and memory request queues. Data ensuing from the request can be re-ordered and presented to the destination based on the current pointer position within the in-order queue.

6463510, Oct 8, 2002

Dec 29, 2000

09/751505

Phillip M. Jones - Spring TX
Robert L. Woods - Allentown PA

Compaq Information Technologies Group, L.P. - Houston TX

G06F 1200

711138, 711141

An apparatus for identifying memory requests originating on remote I/O devices as non-cacheable in a computer system with multiple processors includes a main memory, memory cache, processor, cache coherence directory and cache coherence controller all coupled to a host bridge unit (North bridge). The I/O device transmits requests for data to an I/O bridge unit. The I/O bridge unit forwards the request for data to the host bridge unit and asserts a sideband signal to the host bridge unit if the request is for non-cacheable data. The sideband signal informs the host bridge unit that the memory request is for non-cacheable data and that the cache coherence controller does not need to perform a cache coherence directory lookup. For cacheable data, the cache coherence controller performs a cache coherence directory lookup to maintain the coherence of data stored in a plurality of processor caches in the computer system.

6470429, Oct 22, 2002

Dec 29, 2000

09/752128

Phillip M. Jones - Spring TX
Robert Allan Lester - Tomball TX

Compaq Information Technologies Group, L.P. - Houston TX

G06F 1200

711138, 711141

An apparatus for identifying requests to main memory as non-cacheable in a computer system with multiple processors includes a main memory, memory cache, processor and cache coherence directory all coupled to a host bridge unit (North bridge). The processor transmits requests for data to the main memory via the host bridge unit. The host bridge unit includes a cache coherence controller that implements a protocol to maintain the coherence of data stored in each of the processor caches in the computer system. A cache coherence directory is connected to the cache coherence controller. After receiving the request for data from main memory, the host bridge unit identifies requests for data to main memory as cacheable or non-cacheable. If the data is non-cacheable, then the host bridge unit does not request the cache coherence controller to perform a cache coherence directory lookup to maintain the coherence of the data.

6505260, Jan 7, 2003

Feb 15, 2001

09/784690

Kenneth T. Chin - Cypress TX
C. Kevin Coffee - Pembroke Pines FL
Michael J. Collins - Pleasonton CA
Jerome J. Johnson - Spring TX
Phillip M. Jones - Spring TX
Robert A. Lester - Houston TX
Gary J. Piccirillo - Cypress TX
Jeffrey C. Stevens - Spring TX

Compaq Information Technologies Group, L.P. - Houston TX

G06F 1318

710 41, 710 42, 711151

A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming âmemory-starved. â Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.

6823409, Nov 23, 2004

Sep 28, 2001

09/965894

Phillip M. Jones - Spring TX
Paul B. Rawlins - Spring TX

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 1300

710107, 710 52, 710305, 710306, 711146

A mechanism for efficiently filtering snoop requests in a multi-processor bus system. Specifically, a snoop filter is provided to filter unnecessary snoops in a multi-bus system.

6829665, Dec 7, 2004

Sep 28, 2001

09/965871

Phillip M. Jones - Spring TX
Paul B. Rawlins - Spring TX
Kenneth T. Chin - Cypress TX

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 1300

710107, 710305, 710306, 711146

A technique for optimizing cycle time in maintaining cache coherency. Specifically, a method and apparatus are provided to optimize the processing of requests in a multi-processor-bus system which implements a snoop-based coherency scheme. The acts of snooping a bus for a first address and searching a posting queue for the next address to be snooped are performed simultaneously to minimize the request cycle time.

6848015, Jan 25, 2005

Nov 30, 2001

09/998514

Phillip M. Jones - Spring TX, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F 1314

710311, 710306

A computer system including multiple CPUs inform other logic in a computer system as to the priority level (e. g. , task priority) associated with the CPU or software executing thereon. The logic makes arbitration decisions regarding CPU transactions based, at least in part, on the task priorities of the various CPUs. The logic that implements this technique may be a host bridge within a computer system having multiple CPUs or in a switch or router that interconnects multiple nodes or computer systems.

6961800, Nov 1, 2005

Sep 28, 2001

09/967155

Robert A. Lester - Tomball TX, US
Kenneth T. Chin - Cypress TX, US
Jim Blocker - Cypress TX, US
John E. Larson - Houston TX, US
Phillip M. Jones - Spring TX, US
Paul B. Rawlins - Spring TX, US

Hewlett-Packard Development Company, L.P. - Houston TX

G06F013/36

710306, 710310

Methods for improving processor performance. Specifically, by reducing some of the latency cycles within a host controller, request processing speed can be improved. One technique for improving processing speed involves initiating a deferred reply transaction before the data is available from a memory controller. A second technique involves anticipating the need to transition from a block next request (BNR) state to a bus priority request (BPRI) state, thereby eliminating the need to wait for a request check to determine if the BPRI state must be implemented.