Philip A Bourekas

6598050, Jul 22, 2003

Feb 11, 2000

09/503008

Philip A. Bourekas - San Jose CA

Integrated Device Technology, Inc. - Santa Clara CA

G06F 1730

707100, 711203

An enhanced translation lookaside buffer (TLB), which translates a virtual address into a physical address, permits sharing of data or programs among a subset of all tasks through the use of a group membership field. Each entry in the TLB includes a global bit indicating that all tasks should have access to the translation, an address space identifier identifying an individual task that should have access to the translation and a group membership field identifying a group of tasks that have access to the entry, wherein the group of tasks is a subset of all tasks. The virtual address also has a group membership field that is compared with a group membership field in the TLB entry. If the two group membership fields match, the current task is permitted to use the translation. Thus, a given translation within the TLB may be valid for all tasks, only an individual task, or a group of tasks.

7133951, Nov 7, 2006

Feb 29, 2000

09/515358

Philip A. Bourekas - San Jose CA, US

G06F 13/24

710260, 710261, 710262, 710263, 710264, 710265, 710266, 710316, 710317

A processor includes a set of general purpose registers that are used when executing generic tasks and a set of exception registers that is dedicated for servicing specific exceptions. When a task is interrupted with an asserted “fast” exception, the processor automatically diverts the exception to the dedicated exception registers using a dedicated vector. The dedicated vector and exception registers may be reserved for high priority, i. e. , critical, exceptions. Because the exception registers are automatically activated for fast exceptions, there is no need to determine the priority of the exception. Further, high priority interrupts and high priority operating system calls (traps) may have different dedicated vectors and the set of exception registers may have a portion allocated for servicing interrupts and another portion allocated for servicing operating system calls. With the use of a dedicated vector or dedicated vectors, there is no need for software to decode the fast exception. Advantageously, during the servicing of the exception, the values of the exception registers may be modified, without disrupting the state of the interrupted task.

58941762, Apr 13, 1999

May 4, 1994

8/238192

Philip A. Bourekas - San Jose CA
Avigdor Willenz - Campbell CA
Yeshayahu Mor - Cupertino CA

Integrated Device Technology, Inc. - Santa Clara CA

H03K 302

327198

A structure and a method are provided to implement a reset scheme for an integrated circuit supporting a variety of testing and debugging equipment. The control and I/O pins of the integrated circuit are each set to a high impedance state when the signals of a reset pin and a mode pin are both asserted. If the signal on the mode pin remains asserted at the time the signal on the reset pin is negated, the control and I/O pins of the integrated circuit remain in the high impedance state until the next time the signal on the reset pin is asserted. Otherwise, the control and I/O pins of the integrated circuits are enabled upon negation of the signal on the reset pin. In one embodiment, the mode pin is multiplexed with an pin used for receiving interrupt signals during functional operation.

53177118, May 31, 1994

Jun 14, 1991

7/715526

Philip A. Bourekas - San Jose CA
Yeshayahu Mor - Cupertino CA
Scott Revak - Castro Valley CA

Integrated Device Technology, Inc. - Santa Clara CA

G01R 3128

395425

A structure and a method are provided to bring internal signals of an integrated circuit to the external pins for monitoring purpose. In one embodiment, the signals on an internal bus between an on-chip cache and a CPU in a microprocessor are provided on the microprocessor's pins for a bidirectional data/address bus, when the bidirectional data/address bus is not used for data/address bus transactions with the main memory or the peripheral input/output devices. In this embodiment, reserved pins are used to selectively enable the address/data bus for bringing out the signals of the on-chip bus.

51758598, Dec 29, 1992

May 1, 1990

7/517293

Michael J. Miller - Saratoga CA
Philip A. Bourekas - Sunnyvale CA
Avigdor Willenz - Campbell CA

Integrated Device Technology, Inc. - Santa Clara CA

G06F 122

395800

A method of programming a cache tag comparator by designing a semiconductor device's internal circuitry such that an input/output pin of the device may be programmed by an external resistor to ground that will indicate during the reset phase of the device that an alternate function for the pin is to be selected or that the pin itself is to be disabled.

53434358, Aug 30, 1994

Jun 14, 1991

7/715293

Philip A. Bourekas - San Jose CA
Danh L. Ngoc - Saratoga CA
Scott Revak - Castro Valley CA

Integrated Device Technology, Inc. - Santa Clara CA

G11C 1928

365221

Using a separate data register effectively increases the efficiency of an on-chip write buffer implemented as a FIFO structure. The separate register holds the output data during write cycles, allowing the write buffer FIFO to make the space consumed by the current write available at the start, rather than at the end of the write cycle. This effectively makes the write buffer "four and one-half" entries deep, thereby increasing performance of the buffer without adding additional FIFO entries.

56945671, Dec 2, 1997

Feb 9, 1995

8/386025

Philip A. Bourekas - San Jose CA
Andrew P. Ng - Mountain View CA

Integrated Device Technology, Inc. - Santa Clara CA

G06F 1200

395403

A direct mapped cache with cache locking according to one embodiment of the present invention includes a physical address latch and a multiplexing means. The multiplexing means receives the physical address from the physical address latch and exchanges a physical address tag bit with a physical address index bit to generate a cache tag address and a cache index address to divide the cache into two halves, each half servicing a contiguous address range of main memory.

55176593, May 14, 1996

May 11, 1994

8/240958

Philip A. Bourekas - San Jose CA
Yeshayahu Mor - Cupertino CA
Scott Revak - Castro Valley CA
Avigdor Willenz - Campbell CA

Integrated Device Technology, Inc. - Santa Clara CA

G06F 1500

395800

In a microprocessor, two output pins are dedicated to providing information to assist in diagnosing problems relating to internal instruction and data caches or the software executing in the caches. The information on the pins is time-multiplexed. In a first phase, the pins indicate whether the data or instruction cache is accessed and whether a cache miss has occurred. In a second phase, the pins carry signals identifying the address reference which resulted in a cache miss.