Resumes
Resumes
Petro Estakhri Phones & Addresses
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257 Red Pine Ct, Danville, CA 94506 (925) 895-4554
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7966 Foothill Knolls Dr, Pleasanton, CA 94588 (925) 846-4893 (925) 846-9366
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Davis, CA
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Fremont, CA
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257 Red Pine Ct, Danville, CA 94506
Work
Position:
Sales Occupations
Education
Degree:
High school graduate or higher
Business Records
Name / Title
Company / Classification
Phones & Addresses
President
AVALANCHE TECHNOLOGY, INC
Mfg Semiconductors/Related Devices
Mfg Semiconductors/Related Devices
46600 Lndg Pkwy, Fremont, CA 94538
48371 Fremont Blvd, Fremont, CA 94538
48371 Fremont Blvd, Fremont, CA 94538
Lex Capital, LLC
Investments
Investments
7966 Foothill Knl Dr, Pleasanton, CA 94588
Chief Executive Officer, Principal
Avalanche Technology
Ret Computers/Software
Ret Computers/Software
48430 Lakeview Blvd, Fremont, CA 94538
Chief Executive Officer
Yadav Technology, Inc
Non-Volatile Low Power Memory
Non-Volatile Low Power Memory
48371 Fremont Blvd, Fremont, CA 94538
Board of Directors
Construction Navigator Inc
Software Development
Software Development
48430 Lakeview Blvd, Fremont, CA 94538
(510) 445-1106
(510) 445-1106
LEXAR MEDIA, INC
47300 Bayside Pkwy, Fremont, CA 94538
President
KABOBI RESTAURANT
620 G St BOX 21, Davis, CA 95616
Publications
Us Patents
Data Pipelining Method And Apparatus For Memory Control Circuit
View pageUS Patent:
6374337, Apr 16, 2002
Filed:
Nov 16, 1999
Appl. No.:
09/440986
Inventors:
Petro Estakhri - Pleasanton CA
Assignee:
Lexar Media, Inc. - Fremont CA
International Classification:
G06F 1200
US Classification:
711169, 711100, 711103, 711154, 36518901, 36518905
Abstract:
A method and circuit for fast memory access (read or write) of the data to and from a memory array is disclosed. Architecture wise, the memory array control circuit provides for at least two address latches and two page registers. The first address latch contains a first data address and the second address latch contains a second data address. The first data address is decoded first and sent to the memory array to access (read or write) the corresponding data from the memory array. When the data of the first data address is being accessed, the decoding process will begin for a second data address. When the data of the first data address has been accessed, the second data address is ready for the memory array. Thus, there can be continuous fetching from or writing to the memory array. In the preferred embodiment, there are two page registers.
Identification And Verification Of A Sector Within A Block Of Mass Storage Flash Memory
View pageUS Patent:
6393513, May 21, 2002
Filed:
Apr 23, 2001
Appl. No.:
09/841522
Inventors:
Petro Estakhri - Pleasanton CA
Berhanu Iman - Sunnyvale CA
Berhanu Iman - Sunnyvale CA
Assignee:
Lexar Media, Inc. - Fremont CA
International Classification:
G06F 1210
US Classification:
711103, 711203, 714 42, 714 52
Abstract:
A method and apparatus is disclosed for identifying a block being stored within flash memory devices using a cluster address for each block, the block being selectively erasable and having one or more sectors, the cluster address being stored in one of the sectors of the block. In an alternative embodiment, the cluster address is stored in at least two different sectors within the same block for ensuring that the information last written to the block is valid. Further disclosed is a novel way to use a defect flag for each block stored within the flash memory device for efficiently identifying non-defective blocks upon system power-up.
Increasing The Memory Performance Of Flash Memory Devices By Writing Sectors Simultaneously To Multiple Flash Memory Devices
View pageUS Patent:
6397314, May 28, 2002
Filed:
Nov 2, 2000
Appl. No.:
09/705474
Inventors:
Petro Estakhri - Pleasanton CA
Berhanu Iman - Sunnyvale CA
Berhanu Iman - Sunnyvale CA
Assignee:
Lexar Media, Inc. - Fremont CA
International Classification:
G06F 1200
US Classification:
711168, 711103, 711 5, 711202, 36518904, 36523003
Abstract:
In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored. The storage system includes a memory controller coupled to the host; and a nonvolatile memory bank coupled to the memory controller via a memory bus, the memory bank being included in a non-volatile semiconductor memory unit, the memory bank has storage blocks each of which includes a first row-portion located in said memory unit, and a corresponding second row-portion located in each of the memory unit, each of the memory row-portions provides storage space for two of said sectors, wherein the speed of performing write operations is increased by writing sector information to the memory unit simultaneously.
Precision Clock Synthesizer Using Rc Oscillator And Calibration Circuit
View pageUS Patent:
6404246, Jun 11, 2002
Filed:
Dec 20, 2000
Appl. No.:
09/741971
Inventors:
Petro Estakhri - Pleasanton CA
Mahmud Assar - Morgan Hill CA
Parviz Keshtbod - Los Altos Hills CA
Mahmud Assar - Morgan Hill CA
Parviz Keshtbod - Los Altos Hills CA
Assignee:
Lexa Media, Inc. - Fremont CA
International Classification:
H03L 706
US Classification:
327156, 327147
Abstract:
A system and method of generating an output signal of very precise frequency without the use of a crystal oscillator. An input signal is generated using any convenient such as an RC oscillator. A circuit for producing a frequency-controlled output signal comprises a phase lock loop having a VCO and a down counter. The down counter reduces the frequency of a VCO clock signal in accordance with a down count value. The down count value is loaded in a register and stored in non-volatile memory. The down count value is set during a calibration operation using a precision external clock signal. In this way, a clock signal with a highly precise frequency is generated without using a crystal oscillator.
Nonvolatile Memory Using Flexible Erasing Methods And Method And System For Using Same
View pageUS Patent:
6411546, Jun 25, 2002
Filed:
May 5, 2000
Appl. No.:
09/565517
Inventors:
Petro Estakhri - Pleasanton CA
Siamack Nemazie - San Jose CA
Mahmud Assar - Morgan Hill CA
Parviz Keshtbod - Los Altos CA
Siamack Nemazie - San Jose CA
Mahmud Assar - Morgan Hill CA
Parviz Keshtbod - Los Altos CA
Assignee:
Lexar Media, Inc. - Fremont CA
International Classification:
G11C 1604
US Classification:
36518511, 36518529, 365218
Abstract:
An embodiment of the present invention is disclosed to include a nonvolatile memory system for controlling erase operations performed on a nonvolatile memory array comprised of rows and columns, the nonvolatile memory array stores digital information organized into blocks with each block having one or more sectors of information and each sector having a user data field and an extension field and each sector stored within a row of the memory array. A controller circuit is coupled to a host circuit and is operative to perform erase operations on the nonvolatile memory array, the controller circuit erases an identified sector of information having a particular user data field and a particular extension field wherein the particular user field and the particular extension field are caused to be erased separately.
Block Management For Mass Storage
View pageUS Patent:
6567307, May 20, 2003
Filed:
Feb 28, 2002
Appl. No.:
10/086462
Inventors:
Petro Estakhri - Pleasanton CA
Assignee:
Lexar Media, Inc. - Fremont CA
International Classification:
G11C 1600
US Classification:
36518511, 36523003
Abstract:
An embodiment of the present invention includes a nonvolatile memory system comprising nonvolatile memory for storing sector information, the nonvolatile memory being organized into blocks with each block including a plurality of sectors, each sector identified by a logical block address and for storing sector information. A controller is coupled to the nonvolatile memory for writing sector information to the latter and for updating the sector information, wherein upon updating sector information, the controller writes to the next free or available sector(s) of a block such that upon multiple re-writes or updating of sector information, a plurality of blocks are substantially filled with sector information and upon such time, the controller rearranges the updated sector information in sequential order based on their respective logical block addresses thereby increasing system performance and improving manufacturing costs of the controller.
Nonvolatile Memory Using Flexible Erasing Methods And Method And System For Using Same
View pageUS Patent:
6587382, Jul 1, 2003
Filed:
Jun 19, 2002
Appl. No.:
10/175928
Inventors:
Petro Estakhri - Pleasanton CA
Siamack Nemazie - San Jose CA
Mahmud Assar - Morgan Hill CA
Parviz Keshtbod - Los Altos CA
Siamack Nemazie - San Jose CA
Mahmud Assar - Morgan Hill CA
Parviz Keshtbod - Los Altos CA
Assignee:
Lexar Media, Inc. - Fremont CA
International Classification:
G11C 1604
US Classification:
36518529, 36518511, 365218, 36523003
Abstract:
An embodiment of the present invention is disclosed to include a nonvolatile memory system for controlling erase operations performed on a nonvolatile memory array comprised of rows and columns, the nonvolatile memory array stores digital information organized into blocks with each block having one or more sectors of information and each sector having a user data field and an extension field and each sector stored within a row of the memory array. A controller circuit is coupled to a host circuit and is operative to perform erase operations on the nonvolatile memory array, the controller circuit erases an identified sector of information having a particular user data field and a particular extension field wherein the particular user field and the particular extension field are caused to be erased separately.
Flash Memory Card With Enhanced Operating Mode Detection And User-Friendly Interfacing System
View pageUS Patent:
6721819, Apr 13, 2004
Filed:
Aug 28, 2001
Appl. No.:
09/940972
Inventors:
Petro Estakhri - Pleasanton CA
Mahmud Assar - Morgan Hill CA
Mahmud Assar - Morgan Hill CA
Assignee:
Lexar Media, Inc. - Fremont CA
International Classification:
G06F 1300
US Classification:
710 11, 740 2, 740 8, 740 62, 740 72, 714 3
Abstract:
An interfacing system facilitating user-friendly connectivity in a selected operating mode between a host computer system and a flash memory card. The interfacing system includes an interface device and a flash memory card. The interfacing system features significantly expanded operating mode detection capability within the flash memory card and marked reduction in the incorrect detection of the operating mode. The interface device includes a first end for coupling to the host computer and a second end for coupling to the flash memory card, while supporting communication in the selected operating mode which is also supported by the host computer system. The flash memory card utilizes a fifty pin connection to interface with the host computer system through the interface device. The fifty pin connection of the flash memory card can be used with different interface devices in a variety of configurations such as a universal serial mode, PCMCIA mode, and ATA IDE mode. Each of these modes of operation require different protocols.