Peter M Pani

6417690, Jul 9, 2002

Jun 1, 1998

09/089298

Benjamin S. Ting - Saratoga CA
Peter M. Pani - Mountain View CA

BTR, Inc. - Reno NV

G06F 900

326 41, 712 37, 712 38

A programmable logic device which incorporates an innovative routing hierarchy consisting of the multiple levels of routing lines, connector tab networks and turn matrices, enables an innovative, space saving floor plan to be utilized in an integrated circuit implementation, and is particularly efficient when an SRAM is used as the configuration bit. This floor plan is a scalable block architecture in which each block connector tab networks of a 2Ã2 block grouping is arranged as a mirror image along the adjacent axis relative to each other. Furthermore, the bidirectional input/output lines are provided as the input/output means for each block are oriented only in two directions such that the block connector tab networks for adjacent blocks face each other in orientation. This orientation and arrangement permits blocks to share routing resources. In addition, this arrangement permits blocks to share routing resources.

6504399, Jan 7, 2003

Sep 24, 2001

09/960916

Peter M. Pani - Mountain View CA
Benjamin S. Ting - Saratoga CA

Advantage Logic, Inc. - Cupertino CA

H03K 19177

326 41, 326 38, 326 39, 326 40

The system and method of the present invention provides an innovative bus system of lines which can be programmed and to provide data, control and address information to the logic circuits interconnected by the bus system. This flexible structure and process enables a configurable system to be created to programmably connect one or more logic circuits, such as megacells. The programmability of the bus system enables the cascading of multiple megacells in an arbitrary fashion (i. e. , wide, deep or both) and the sharing of common lines for system level communication.

6624658, Sep 23, 2003

Aug 28, 2002

10/231320

Peter M. Pani - Mountain View CA
Benjamin S. Ting - Saratoga CA

Advantage Logic, Inc. - Cupertino CA

H03K 19177

326 41, 326 38, 326 39

The system and method of the present invention provides an innovative bus system of lines which can be programmed and to provide data, control and address information to the logic circuits interconnected by the bus system. This flexible structure and process enables a configurable system to be created to programmably connect one or more logic circuits, such as megacells. The programmability of the bus system enables the cascading of multiple megacells in an arbitrary fashion (i. e. , wide, deep or both) and the sharing of common lines for system level communication.

6781410, Aug 24, 2004

Apr 11, 2003

10/412975

Peter M. Pani - Mountain View CA
Benjamin S. Ting - Saratoga CA

Advantage Logic, Inc. - Cupertino CA

H03K 19177

326 41, 326 38, 326 39

The system and method of the present invention provides an innovative bus system of lines which can be programmed and to provide data, control and address information to the logic circuits interconnected by the bus system. This flexible structure and process enables a configurable system to be created to programmably connect one or more logic circuits, such as megacells. The programmability of the bus system enables the cascading of multiple megacells in an arbitrary fashion (i. e. , wide, deep or both) and the sharing of common lines for system level communication.

6975138, Dec 13, 2005

Mar 25, 2004

10/811422

Peter M. Pani - Mountain View CA, US
Benjamin S. Ting - Saratoga CA, US

Advantage Logic, Inc. - Cupertino CA

H03K019/177

326 41, 326 38, 326 39

A programmable logic device is described having an internal three-statable bus and a plurality of driving elements coupled to the internal three-statable bus. Each of the driving elements is operable to drive the internal three-statable bus. The programmable logic device also includes a plurality of interface logic circuits with each of the plurality of interface logic circuits coupled to a different one of the plurality of driving elements. Each interface logic circuit is operable to determine whether the internal three-statable bus is being driven and the interface logic circuits are collectively operable to prevent contention of signals on the internal three-statable bus.

6975139, Dec 13, 2005

Mar 30, 2004

10/814943

Peter M. Pani - Mountain View CA, US
Benjamin S. Ting - Saratoga CA, US

Advantage Logic, Inc. - Cupertino CA

H03K019/177

326 41, 326 47, 326101

A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, be construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.

7009422, Mar 7, 2006

Dec 5, 2001

10/021744

Benjamin S. Ting - Saratoga CA, US
Peter M. Pani - Mountain View CA, US

BTR, Inc. - Reno NE

G06F 9/00

326 41, 712 37, 712 38

A programmable logic device which incorporates an innovative routing hierarchy consisting of the multiple levels of routing lines, connector tab networks and turn matrices, enables an innovative, space saving floor plan to be utilized in an integrated circuit implementation, and is particularly efficient when an SRAM is used as the configuration bit This floor plan is a scalable block architecture in which each block connector tab networks of a 2×2 block grouping is arranged as a mirror image along the adjacent axis relative to each other. Furthermore, the bidirectional input/output lines are provided as the input/output means for each block are oriented only in two directions (instead of the typical north, south, east and west directions) such that the block connector tab networks for adjacent blocks face each other in orientation. This orientation and arrangement permits blocks to share routing resources. In addition, this arrangement enables a 4×4 block grouping to be scalable.

7126375, Oct 24, 2006

Jan 4, 2006

11/326543

Benjamin S. Ting - Saratoga CA, US
Peter M. Pani - Mountain View CA, US

BTR, Inc. - Reno NV

G06F 9/00

326 41, 712 37, 712 38

A multiple level routing architecture for a programmable logic device having logical blocks, each logical block comprising a plurality of cells, with a first level routing resources coupling the cells of logical blocks. A second level routing resources coupling the first level routing resources through tab networks; each tab network comprises a first plurality of switches coupling the first level routing resources to an intermediate tab and the intermediate tab coupling the second level routing resources through a second plurality of switches, each switch may comprise an additional buffer. Repeated applications of tab networks provide connections between lower level routing resources to higher level routing resources.