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Peter R Keswick

from Bloomington, MN
Age ~61
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Also known as:
Peter Chrisanne Keswick, Keswick Keswick
Phone and address:
10304 Morris Rd, Minneapolis, MN 55437
(952) 841-9164
Related to:
Thomas A Keswick, 43Christy Everett, 42Arthur L Keswick, 99Kathryn A Keswick, 94Natalie A Keswick, 34Chrisanne F Keswick, 61Kathryn Keswick, 72
Connected to:
Shawn P Keswick, 47Geza Keszei, 88Allison Keszenheimer, 44Jennifer N Keszler, 48Lauren Keszler, 29Narin N Ket, 52Sarah S Ket, 59Christine Keta, 44Evan M Ketabchi, 38Hassan A Ketana, 64

Peter Keswick Phones & Addresses

  • 10304 Morris Rd, Bloomington, MN 55437 (952) 841-9164
  • 10304 Morris Ave, Bloomington, MN 55437 (952) 841-9164
  • Minneapolis, MN
  • Fremont, CA
  • Rock Island, IL
  • San Jose, CA
  • Newark, CA

Work

Company: Sageglass Oct 1, 2008 Position: Senior process development engineer at sage electrochromics, inc

Education

Degree: Master of Science, Masters School / High School: University of California, Berkeley 1986 to 1989

Skills

Design of Experiments • Semiconductors • Process Engineering • R&D • Engineering • Jmp • Process Simulation • Fmea • Thin Films • Coatings • Six Sigma • Yield • Spc • Lean Manufacturing • Failure Analysis • Process Integration • Six Sigma Black Belt • Glass Coating

Industries

Building Materials

Resumes

Resumes

Peter Keswick Photo 1

Senior Process Development Engineer At Sage Electrochromics, Inc

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Location:
Minneapolis, MN
Industry:
Building Materials
Work:
Sageglass
Senior Process Development Engineer at Sage Electrochromics, Inc
Cypress Semiconductor Corporation 2006 - 2008
Principle Yield Engineer
Cypress Semiconductor Corporation 1999 - 2006
Senior R and D Manager
Cypress Semiconductor Corporation 1997 - 1999
Staff Technology Development Engineer
Applied Materials 1995 - 1997
Process Engineering Manager
Education:
University of California, Berkeley 1986 - 1989
Master of Science, Masters University of California, Berkeley 1982 - 1986
Bachelors, Bachelor of Science
Skills:
Design of Experiments
Semiconductors
Process Engineering
R&D
Engineering
Jmp
Process Simulation
Fmea
Thin Films
Coatings
Six Sigma
Yield
Spc
Lean Manufacturing
Failure Analysis
Process Integration
Six Sigma Black Belt
Glass Coating

Publications

Us Patents

High Temperature Silicon Surface Providing High Selectivity In An Oxide Etch Process

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US Patent:
6399514, Jun 4, 2002
Filed:
Aug 24, 2000
Appl. No.:
09/645924
Inventors:
Jeffrey Marks - San Jose CA
Jerry Yuen-Kui Wong - Fremont CA
David W. Groechel - Sunnyvale CA
Peter R. Keswick - Newark CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21302
US Classification:
438729, 438711, 438714, 438719, 438723, 216 71, 216 79, 216 80
Abstract:
A plasma process for etching oxide and having a high selectivity to silicon including flowing into a plasma reaction chamber a fluorine-containing etching gas and maintaining a temperature of an exposed silicon surface within said chamber at a temperature of between 200Â C. and 300Â C. An example of the etching gas includes SiF and a fluorocarbon gas. The plasma may be generated by a capacitive discharge type plasma generator or by an electromagnetically coupled plasma generator, such as an inductively coupled plasma generator. The high selectivity exhibited by the etch process permits use of an electromagnetically coupled plasma generator, which in turn permits the etch process to be performed at low pressures of between 1 and 30 milliTorr, resulting the etching of vertical sidewalls in the oxide layer.

Plasma Reactor With Heated Source Of A Polymer-Hardening Precursor Material

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US Patent:
6440866, Aug 27, 2002
Filed:
Jun 16, 2000
Appl. No.:
09/595750
Inventors:
Kenneth S. Collins - San Jose CA
Michael Rice - Pleasanton CA
David W. Groechel - Los Altos Hills CA
Gerald Zheyao Yin - Cupertino CA
Jon Mohn - Saratoga CA
Craig A. Roderick - San Jose CA
Douglas Buchberger - Tracy CA
Jeffrey Marks - San Jose CA
Peter Keswick - Fremont CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 2100
US Classification:
438714, 156345, 216 67, 216 68, 438715, 438723, 438738, 438743
Abstract:
A general method of the invention is to provide a polymer-hardening precursor piece (such as silicon, carbon, silicon carbide or silicon nitride, but preferably silicon) within the reactor chamber during an etch process with a fluoro-carbon or fluoro-hydrocarbon gas, and to heat the polymer-hardening precursor piece above the polymerization temperature sufficiently to achieve a desired increase in oxide-to-silicon etch selectivity. Generally, this polymer-hardening precursor or silicon piece may be an integral part of the reactor chamber walls and/or ceiling or a separate, expendable and quickly removable piece, and the heating/cooling apparatus may be of any suitable type including apparatus which conductively or remotely heats the silicon piece.

Method For Processing Substrates Using Gaseous Silicon Scavenger

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US Patent:
6444137, Sep 3, 2002
Filed:
Jul 1, 1996
Appl. No.:
08/673972
Inventors:
Kenneth S. Collins - San Jose CA
Jerry Yuen-Kui Wong - Fremont CA
Jeffrey Marks - San Jose CA
Peter R. Keswick - Newark CA
David W. Groechel - Sunnyvale CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
C23F 100
US Classification:
216 79, 216 67, 216 68
Abstract:
A plasma reactor chamber uses an antenna driven by RF energy (LF, MF, or VHF) which is inductively coupled inside the reactor dome. The antenna generates a high density, low energy plasma inside the chamber for etching oxygen-containing layers overlying non-oxygen-containing layers with high selectivity. Auxiliary RF bias energy applied to the wafer support cathode controls the cathode sheath voltage and controls the ion energy independent of density. Various magnetic and voltage processing enhancement techniques are disclosed, along with other etch processes, deposition processes and combined etch/deposition processes. The disclosed invention provides processing of sensitive devices without damage and without microloading, thus providing increased yields. Etching of an oxygen-containing layer overlying a non-oxygen-containing layer can be achieved with high selectivity.

Magnetic Confinement In A Plasma Reactor Having An Rf Bias Electrode

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US Patent:
6488807, Dec 3, 2002
Filed:
May 3, 2000
Appl. No.:
09/563825
Inventors:
Kenneth S. Collins - San Jose CA
Jerry Yuen-Kui Wong - Fremont CA
Jeffrey Marks - San Jose CA
Peter R. Keswick - Bloomington MN
David W. Groechel - Los Altos Hills CA
Craig A. Roderick - San Jose CA
John R. Trow - San Jose CA
Tetsuya Ishikawa - Chiba, JP
Lawrence Chang-Lai Lei - Cupertino CA
Masato M. Toshima - Sunnyvale CA
Gerald Zheyao Yin - Cupertino CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H05H 100
US Classification:
15634549, 15634548, 118723 I
Abstract:
The invention is embodied in an RF plasma reactor for processing a semiconductor workpiece, including wall structures for containing a plasma therein, a workpiece support, a coil antenna capable of receiving a source RF power signal and being juxtaposed near the chamber, the workpiece support including a bias electrode capable of receiving a bias RF power signal, and first and second magnet structures adjacent the wall structure and in spaced relationship, with one pole of the first magnet structure facing an opposite pole of the second magnet structure, the magnet structures providing a plasma-confining static magnetic field adjacent said wall structure. The invention is also embodied in an RF plasma reactor for processing a semiconductor workpiece, including one or more wall structures for containing a plasma therein, a workpiece support, the workpiece support comprising a lower electrode, an upper electrode facing the lower electrode and spaced across a plasma generation region of said chamber from said lower electrode, and first and second magnet structures adjacent the wall structure and in spaced relationship with one pole of the first magnet structure facing an opposite pole of the second magnet structure, the magnet structures providing a plasma-confining static magnetic field adjacent said wall structure.

Plasma Reactor Using Inductive Rf Coupling, And Processes

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US Patent:
6518195, Feb 11, 2003
Filed:
Feb 15, 2000
Appl. No.:
09/504312
Inventors:
Kenneth S. Collins - San Jose CA
Jerry Yuen-Kui Wong - Fremont CA
Jeffrey Marks - San Jose CA
Peter R. Keswick - Bloomington MN
David W. Groechel - Los Altos Hills CA
Craig A. Roderick - San Jose CA
John R. Trow - San Jose CA
Tetsuya Ishikawa - Chiba, JP
Lawrence Chang-Lai Lei - Cupertino CA
Masato M. Toshima - Sunnyvale CA
Gerald Zheyao Yin - Cupertino CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 213065
US Classification:
438723, 438729, 438743
Abstract:
A domed plasma reactor chamber uses an antenna driven by RF energy (LF, MF, or VHF) which is inductively coupled inside the reactor dome. The antenna generates a high density, low energy plasma inside the chamber for etching metals, dielectrics and semiconductor materials. Auxiliary RF bias energy applied to the 10 wafer support cathode controls the cathode sheath voltage and controls the ion energy independent of density. Various magnetic and voltage processing enhancement techniques are disclosed, along with etch processes deposition processes and combined etch/deposition processed. The disclosed invention provides processing of sensitive devices without damage and without microloading, thus providing increased yields.

Plasma Reactor Using Inductive Rf Coupling, And Processes

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US Patent:
6545420, Apr 8, 2003
Filed:
Jun 6, 1995
Appl. No.:
08/468573
Inventors:
Kenneth S. Collins - San Jose CA
Craig A. Roderick - San Jose CA
John R. Trow - Santa Clara CA
Jerry Yuen-Kui Wong - Fremont CA
Jeffrey Marks - San Jose CA
Peter R. Keswick - Newark CA
David W. Groechel - Sunnyvale CA
Tetsuya Ishikawa - Chiba, JP
Lawrence Chang-Lai Lei - Cupertino CA
Masato M. Toshima - Sunnyvale CA
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01J 724
US Classification:
31511151, 118723 ER, 118723 IR, 118723 I
Abstract:
A domed plasma reactor chamber uses an antenna driven by RF energy (LF, MF, or VHF) which is inductively coupled inside the reactor dome. The antenna generates a high density, low energy plasma inside the chamber for etching metals, dielectrics and semiconductor materials. Auxiliary RF bias energy applied to the wafer support cathode controls the cathode sheath voltage and controls the ion energy independent of density. Various magnetic and voltage processing enhancement techniques are disclosed, along with etch processes, deposition processes and combined etch/deposition processed. The disclosed invention provides processing of sensitive devices without damage and without microloading, thus providing increased yields.

Gate Etch Process

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US Patent:
6699795, Mar 2, 2004
Filed:
Mar 15, 2002
Appl. No.:
10/099841
Inventors:
Benjamin Schwarz - San Jose CA
Kiyoko Ikeuchi - Sunnyvale CA
Peter Keswick - Bloomington MN
Lien Lee - Bloomington MN
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
H01L 21302
US Classification:
438717, 156643, 1566531, 438 72, 438494, 438636, 438689, 438691, 438695, 438712, 438713, 438719, 438720, 438724, 438734, 438738, 438749, 438757, 438952
Abstract:
A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.

Gate Etch Process

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US Patent:
7112834, Sep 26, 2006
Filed:
Mar 2, 2004
Appl. No.:
10/791657
Inventors:
Benjamin Schwarz - San Jose CA, US
Kiyoko Ikeuchi - Sunnyvale CA, US
Peter Keswick - Bloomington MN, US
Lien Lee - Bloomington MN, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L 29/76
US Classification:
257288, 257327, 257368, 257E21001, 438585, 438197, 438710, 438724
Abstract:
A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.
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Peter R Keswick from Bloomington, MN, age ~61 Get Report