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Peter Kamil Charvat

from Portland, OR
Age ~63
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Also known as:
Peter K Charvat, Peter Tr Charvat
Phone and address:
1911 NW Norfolk Ct, Portland, OR 97229
(503) 291-7487
Related to:
Anthony J Charvat, 26Benjamin J Charvat, 60Fedia R Charvat, 94Margaret M CharvatMargaret M Charvat
Connected to:
Ashley P Charvat, 38Jamie A Charvat, 48Mark J Charvat, 70Alejandro Charvel, 75Danielle D Charvet, 30Deborah S Charvet, 68Esteban A Charvet, 48Hunter Charvet, 75Martin J Charvet, 46Michelle Charvet, 50

Peter Charvat Phones & Addresses

  • 1911 NW Norfolk Ct, Portland, OR 97229 (503) 291-7487
  • Sagle, ID
  • La Jolla, CA
  • Bone, ID

Professional Records

Medicine Doctors

Peter Charvat Photo 1

Peter L. Charvat

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Specialties:
Emergency Medicine
Work:
Central Minnesota Emergency Physicians
1406 6 Ave N, Saint Cloud, MN 56303
(320) 255-5656 (phone), (320) 656-7044 (fax)
Education:
Medical School
Saint Louis University School of Medicine
Graduated: 1994
Languages:
English
Description:
Dr. Charvat graduated from the Saint Louis University School of Medicine in 1994. He works in Saint Cloud, MN and specializes in Emergency Medicine. Dr. Charvat is affiliated with Saint Cloud Hospital.

Publications

Us Patents

Anchored Via Connection

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US Patent:
56190719, Apr 8, 1997
Filed:
Aug 15, 1995
Appl. No.:
8/515318
Inventors:
Alan M. Myers - Hillsboro OR
Peter K. Charvat - Portland OR
Thomas A. Letson - Beaverton OR
Peng Bai - Aloha OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23522
H01L 23532
H01L 2941
US Classification:
257753
Abstract:
A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.

Method Of Patterning A Layer For A Gate Electrode Of A Mos Transistor

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US Patent:
61910163, Feb 20, 2001
Filed:
Jan 5, 1999
Appl. No.:
9/226503
Inventors:
Robert S. Chau - Beaverton OR
Thomas Letson - Beaverton OR
Patricia Stokley - Aloha OR
Peter Charvat - Portland OR
Ralph Schweinfurth - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 213205
H01L 214763
US Classification:
438585
Abstract:
A structure is provided comprising a semiconductor substrate, a gate oxide layer on the substrate, and a polysilicon layer on the gate oxide layer. A masking layer is formed on the polysilicon layer. The masking layer is then patterned into a mask utilizing conventional photolithographic techniques, but without patterning the polysilicon layer. The photoresist layer is then removed, whereafter the mask, which is patterned out of the masking layer, is utilized for patterning the polysilicon layer. The use of a carbon free mask for patterning the polysilicon layer, instead of a conventional photoresist layer containing carbon, results in less breakthrough through the gate oxide layer when the polysilicon layer is patterned. Less breakthrough through the gate oxide layer allows for the use of thinner gate oxide layers, and finally fabricated transistors having lower threshold voltages.

High Cf.sub.4 Flow-Reactive Ion Etch For Aluminum Patterning

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US Patent:
52022919, Apr 13, 1993
Filed:
May 8, 1992
Appl. No.:
7/883067
Inventors:
Peter K. Charvat - Portland OR
Chris Kardas - Tigard OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21465
US Classification:
437245
Abstract:
An anisotropic reactive ion etching of an aluminum metal film of a semiconductor device. The device is placed in a reactive ion etcher using a CF. sub. 4, Cl. sub. 2 and BCl. sub. 3 gas mixture to anisotropically etch the aluminum metal film layer wherein the gas mixture has a ratio of CF. sub. 4 :Cl. sub. 2 such that the aluminum etch rate increases as the amount of CF. sub. 4 relative to Cl. sub. 2 increases.

Method For Etching Silicon Oxide Films In A Reactive Ion Etch System To Prevent Gate Oxide Damage

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US Patent:
55497845, Aug 27, 1996
Filed:
Sep 14, 1994
Appl. No.:
8/306251
Inventors:
Kevin F. Carmody - Hillsboro OR
Peter K. Charvat - Portland OR
Gilroy J. Vandentop - Aloha OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2100
US Classification:
1566431
Abstract:
The present invention discloses a method for the etching of insulating films, specifically silicon oxide films, using a fluorine-helium-oxygen gas mixture in the fabrication of semiconductor devices. The method utilizes a prior art reactive ion etch system and adds a quantity of helium to a pre-established fluorine-oxygen chemistry to reactively etch the silicon oxide film while minimizing the occurrence of gate charging resulting from damage to the gate oxide. The addition of helium gas into the etch chemistry must be such that the flow of helium is at least 20% of the sum of the total fluorine, helium, and oxygen flows. The resulting etch chemistry, which can be used in any commercially available reactive ion etch system, produces a more uniform etch while reducing gate oxide damage so as to minimize charging of the semiconductor gate.

Via Hole Profile And Method Of Fabrication

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US Patent:
58743588, Feb 23, 1999
Filed:
Feb 25, 1997
Appl. No.:
8/805961
Inventors:
Alan M. Myers - Hillsboro OR
Peter K. Charvat - Portland OR
Thomas A. Letson - Beaverton OR
Peng Bai - Aloha OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21302
US Classification:
438640
Abstract:
A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.

Dry Process For Stripping Photoresist From A Polyimide Surface

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US Patent:
52622797, Nov 16, 1993
Filed:
Sep 9, 1992
Appl. No.:
7/942322
Inventors:
Chi-Hwa Tsang - Aloha OR
Peter K. Charvat - Portland OR
Robert M. Guptill - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G03C 500
US Classification:
430311
Abstract:
A dry process for stripping photoresist from a polyimide surface formed on a substrate is described. The present invention is practiced after a polyimide layer has been etched. Prior to etching, the polyimide surface is masked with photoresist which is then patterned. The polyimide is etched in exposed regions, for example to form vias to expose contacts located beneath the polyimide layer. The present invention then strips the photoresist in a single wafer downstream plasma etcher in a plasma comprising oxygen radicals. The polyimide is subjected to a short preheat before introduction of the oxygen plasma, and is also heated during the stripping process. The strip proceeds until an endpoint is detected. The endpoint is detected by a change in the spectral emission of the plasma which occurs due to a decrease in the amount of CH. sub. 3 radicals present in the system when the polyimide surface is reached.

Polyimide Process For Protecting Integrated Circuits

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US Patent:
52428648, Sep 7, 1993
Filed:
Jun 5, 1992
Appl. No.:
7/893765
Inventors:
Maxine Fassberg - Beaverton OR
Melton C. Bost - Hillsboro OR
Krishnamurthy Murali - Portland OR
Peter K. Charvat - Portland OR
Lynn A. Price - Portland OR
Robert C. Lindstedt - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21469
US Classification:
437228
Abstract:
A process for forming a protective polyimide layer over a semiconductor substrate includes the steps of curing a deposited polyamic acid layer at a temperature which is sufficient to reduce the etch rate of the acid layer when subsequently exposed to a developer. After formation of a photoresist masking layer over the polyamic acid, the substrate is exposed to a developer to define a plurality of bonding pad openings therein. The developer permeates into the acid layer to form a salt in the regions beneath the openings. Subsequent hardbaking imidizes the polyamic acid, but not the salt regions. Removing the photoresist layer also develops the polyimide which removes the salt regions to expose the underlying bonding pads.

Via Hole Profile And Method Of Fabrication

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US Patent:
54707900, Nov 28, 1995
Filed:
Oct 17, 1994
Appl. No.:
8/324763
Inventors:
Alan M. Myers - Hillsboro OR
Peter K. Charvat - Portland OR
Thomas A. Letson - Beaverton OR
Peng Bai - Aloha OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21302
US Classification:
437192
Abstract:
A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.
Control profile
Peter Kamil Charvat from Portland, OR, age ~63 Get Report