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Peng Yi E Wu

from Wellesley, MA
Age ~70

Peng Wu Phones & Addresses

  • 15 Willow St, Wellesley Hills, MA 02482 (781) 235-5125 (781) 431-1564
  • Wellesley, MA
  • Buffalo, NY
  • Niagara Falls, NY
  • Amherst, NY
  • Tonawanda, NY
  • Cambridge, MA
  • Redfield, AR
  • 15 Willow St, Wellesley, MA 02481 (781) 235-5125

Work

Company: Verizon communications inc. Address: 204 2Nd Ave, Waltham, MA 02451 Phones: (781) 693-3551 Position: Technical expert Industries: Business Associations

Education

Degree: Graduate or professional degree

Emails

Specialities

Foreign Investment • International Trade • Mergers and Acquisitions • Anti-Monopoly and Foreign-Related Commercial Litigation and Arbitration

Professional Records

Lawyers & Attorneys

Peng Wu Photo 1

Peng Wu - Lawyer

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Office:
Zhong Lun Law Firm
Specialties:
Foreign Investment
International Trade
Mergers and Acquisitions
Anti-Monopoly and Foreign-Related Commercial Litigation and Arbitration
ISLN:
909931443
Admitted:
People's Republic of China
Law School:
Graduate School of Kyushu University in Japan, LL.B.; Graduate School of Kyushu University in Japan, LL.M., 1989; Peking University, LL.B., 1984

Resumes

Resumes

Peng Wu Photo 2

It Operations Analyst

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Location:
Wellesley Hills, MA
Industry:
Telecommunications
Work:
Avaya
It Operations Analyst
Peng Wu Photo 3

Peng Wu

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Location:
United States

Business Records

Name / Title
Company / Classification
Phones & Addresses
Peng Wu
Technical Expert
Verizon Communications Inc.
Business Associations
204 2Nd Ave, Waltham, MA 02451
Peng Wu
Technical Expert
Verizon Communications Inc.
204 2 Ave, Waltham, MA 02451
(781) 693-3551
Peng Wu
SAKE THREE, INC
Peng Wu
SAKE AT SPRINGFIELD, INC
Peng Wu
Principal
D & P Asian Corporation
Business Services at Non-Commercial Site
31 Lunt St, Quincy, MA 02171
Peng Wu
Principal
Peng Wu
Business Services at Non-Commercial Site
18 Traill St, Cambridge, MA 02138
Peng Wu
Technical Expert
Verizon Communications Inc.
Business Associations
204 2Nd Ave, Waltham, MA 02451

Publications

Isbn (Books And Publications)

Languages and Compilers for Parallel Computing: 19th International Workshop, LCPC 2006, New Orleans, LA, USA, November 2-4, 2006, Revised Papers

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Author

Peng Wu

ISBN #

3540725202

Us Patents

Synchronous Destage Of Write Data From Shared Global Memory To Back-End Storage Resources

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US Patent:
20220229589, Jul 21, 2022
Filed:
Jan 19, 2021
Appl. No.:
17/151794
Inventors:
- Hopkinton MA, US
Rong Yu - West Roxbury MA, US
Peng Wu - Westborough MA, US
Shao Hu - Westborough MA, US
Mohammed Asher VT - Bangalore, IN
International Classification:
G06F 3/06
Abstract:
A synchronous destage process is used to move data from shared global memory to back-end storage resources. The synchronous destage process is implemented using a client-server model between a data service layer (client) and back-end disk array of a storage system (server). The data service layer initiates a synchronous destage operation by requesting that the back-end disk array move data from one or more slots of global memory to back-end storage resources. The back-end disk array services the request and notifies the data service layer of the status of the destage operation, e.g. a destage success or destage failure. If the destage operation is a success, the data service layer updates metadata to identify the location of the data on back-end storage resources. If the destage operation is not successful, the data service layer re-initiates the destage process by issuing a subsequent destage request to the back-end disk array.

Cache Memory Architecture And Management

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US Patent:
20230021424, Jan 26, 2023
Filed:
Jan 28, 2022
Appl. No.:
17/586901
Inventors:
- Round Rock TX, US
Mark Halstead - Holliston MA, US
Rong Yu - West Roxbury MA, US
Peng Wu - Westborough MA, US
Benjamin Yoder - Chandler AZ, US
Assignee:
Dell Products L.P. - Round Rock TX
International Classification:
G06F 3/06
G06F 12/0831
G06F 12/02
Abstract:
Aspects of the present disclosure relate to data cache management. In embodiments, a logical block address (LBA) bucket is established with at least one logical LBA group. Additionally, at least one LBA group is associated with two or more distinctly sized cache slots based on an input/output (IO) workload received by the storage array. Further, the association includes binding the two or more distinctly sized cache slots with at least one LBA group and mapping the bound distinctly sized cache slots in a searchable data structure. Furthermore, the searchable data structure identifies relationships between slot pointers and key metadata.

Cache Memory Architecture And Management

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US Patent:
20230023314, Jan 26, 2023
Filed:
Jul 26, 2021
Appl. No.:
17/385257
Inventors:
- Hopkinton MA, US
Mark Halstead - Holliston MA, US
Rong Yu - West Roxbury MA, US
Peng Wu - Westborough MA, US
Benjamin Yoder - Chandler AZ, US
Kaustubh Sahasrabudhe - Westborough MA, US
Assignee:
EMC IP Holding Company LLC - Hopkinton MA
International Classification:
G06F 12/0802
G06F 13/20
Abstract:
Aspects of the present disclosure relate to data cache management. In embodiments, a storage array's memory is provisioned with cache memory, wherein the cache memory includes one or more sets of distinctly sized cache slots. Additionally, a logical storage volume (LSV) is established with at least one logical block address (LBA) group. Further, at least one of the LSV's LBA groups is associated with two or more distinctly sized cache slots based on an input/output (IO) workload received by the storage array.

Slice Memory Control

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US Patent:
20210334026, Oct 28, 2021
Filed:
Apr 27, 2020
Appl. No.:
16/859183
Inventors:
- Hopkinton MA, US
Jingtong Liu - Natick MA, US
Peng Wu - Westborough MA, US
Assignee:
EMC IP Holding Company LLC - Hopkinton MA
International Classification:
G06F 3/06
Abstract:
Embodiments of the present disclosure relate to managing communications between slices on a storage device engine. Shared slice memory of a storage device engine is provisioned for use by each slice of the storage device engine. The shared slice memory is a portion of total storage device engine memory. Each slice's access to the shared memory portion is controlled.

Crispr Protein Inhibitors

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US Patent:
20200354701, Nov 12, 2020
Filed:
Oct 31, 2018
Appl. No.:
16/760425
Inventors:
- Cambridge MA, US
- Boston MA, US
- Oakland CA, US
Peng WU - Boston MA, US
Hari SUBRAMANIAN - Oakland CA, US
Elisa FRANCO - Oakland CA, US
International Classification:
C12N 9/22
C12Q 1/6837
Abstract:
The embodiments disclosed herein utilize fluorescence polarization based preliminary screen to identify a putative set of Cas inhibitors from an initial set of candidate inhibitors. The primary screening assay is followed by secondary screening assay to validate the putative set of inhibitors selected by the preliminary screen. In some embodiments, the present disclosure includes compositions and methods are provided for the inhibition of the function of RNA guided endonucleases, including the identification and use of such inhibitors.

Data Deduplication Using Truncated Fingerprints

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US Patent:
20190340262, Nov 7, 2019
Filed:
May 2, 2018
Appl. No.:
15/968825
Inventors:
- Hopkinton MA, US
Rong Yu - West Roxbury MA, US
Peng Wu - Westborough MA, US
Michael J. Scharland - Franklin MA, US
International Classification:
G06F 17/30
Abstract:
The system, devices, and methods disclosed herein relate to data ratio reduction technology adapted to reduce storage costs by weeding out duplicative data write operations. The techniques and systems disclosed achieve deduplication benefits by reducing the size of hash values stored hash tables used to compare unwritten data blocks to data that has already been written and stored somewhere in physical storage. The data deduplication systems, methods, and products facilitate deduplication at the block level as well as for misaligned data chunks within data blocks, that is an unwritten data block that has been stored sequentially in two different physical locations. The deduplication teachings herein are amenable to varying data block sizes as well as data chunk sizes within blocks. Our embodiments enhance computer performance by substantially reducing computational speeds and storage requirements attendant to deduplication systems using larger hash table data sizes.

Unification Of Descriptive Programming And Object Repository

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US Patent:
20160019129, Jan 21, 2016
Filed:
Jul 16, 2014
Appl. No.:
14/333036
Inventors:
- Arlington VA, US
Peng Wu - Wellesley MA, US
International Classification:
G06F 11/30
Abstract:
A computer device may include logic configured to provide a centralized library for descriptive programming and other types of object descriptions to a testing script engine. The descriptive programming library may store test object descriptions for test objects associated with an application under testing. The logic may be further configured to provide a unification layer over all the object description types and to provide inheritance among the objects at the unification layer. The logic may be further configured to store a test object description, associated with a test object, in the descriptive programming library; identify a reference to the test object in a descriptive programming statement associated with the testing script engine; access the stored test object description in the descriptive programming library based on the identified reference to the test object; and identify an application object, associated with the application under testing, based on the stored test object description.
Peng Yi E Wu from Wellesley, MA, age ~70 Get Report